Go below .5V with SRAM from sureCore
April 05, 2023
News
sureCore has designed the PowerMiser Plus, a new family of ultra-low voltage SRAM solutions that are operational down to 0.45V. Performance, as well as power consumption, are able to be increased and decreased concurrently by the logic and memory interfacing at equivalent voltages.
Paul Wells, sureCore’s founder and CEO says, “More and more customers are responding to market pressures to deliver extended battery lives. In doing so, they can no longer ignore the significant power drain of their embedded SRAM. This is especially true in the edge-AI space where pattern matching requires heavy SRAM usage.”
sureCore’s sureFIT, delivers memory sub-system environments developed for the 3D design space of Power, Performance and Area (PPA). sureCore memories deliver single rail, low voltage operation enabling direct logic connection with simplistic system level designs.
According to sureCore, “For one customer, sureCore ported the PowerMiser Plus architecture to a leading 12nm process interfacing to logic operating at 0.45V whilst delivering 400MHz performance at the worst-case corner. The SoC had an on-chip LDO generating both the logic supply as well as a 0.65V supply for the SRAM storage arrays. This ensured that as system level shifts in operating voltage were made so as to meet the required performance targets, then the two supplies tracked each other within a predefined margin. This meant that the use of power-hungry level shifters within the SRAM were avoided, thereby further optimizing power consumption.”
For more information, visit sure-core.com.
Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.
He is well versed in many facets of industrial computing including Edge AI, IoT, Processing, Security, Open Source, and more.
Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.
