Avery Design Systems Announces Verification Support for New UCIe Standard, Speeding Up Chiplet Interconnect Protocol Adoption

By Chad Cox

Embedded Computing Design

June 23, 2022

News

Avery Design Systems Announces Verification Support for New UCIe Standard, Speeding Up Chiplet Interconnect Protocol Adoption
Image Provided by Avery Design Systems

Avery Design Systems announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, allowing design and verification engineers to take advantage of the recently introduced standard for die-to-die interface connectivity. Avery's offering includes high-quality models and test suites for UCIe-based system pre-silicon verification.

As part of its commitment to the standard, Avery has joined the UCIe consortium, which includes founding members Intel, AMD, Arm, Qualcomm, TSMC, Samsung, ASE, Google, Microsoft, and Meta.

UCIe was announced earlier this year as a means of enabling chiplet interoperability within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. The initial specification (Version 1.0) focuses on the UCIe Adapter and PHY, including the die-to-die I/O physical layer, Die-to-Die protocols, and software stack, all of which leverage the well-established PCI Express® (PCIe®) and Compute Express LinkTM (CXLTM) industry standards, as well as a protocol-agnostic raw transfer mode.

Based on its robustly tested verification IP (VIP) portfolio, Avery provides a complete functional verification platform that enables pre-silicon validation of design elements. Its UCIe offering includes a standalone UCIe die to die adapter and LogPHY verification, as well as integrated PCIe and CXL VIP for use over the UCIe stack. It provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test-suites, in addition to UCIe models, through a flexible and open architecture.

“As the use of various packaging methods evolves and grows, we are excited to be involved at the ground floor of this important new standard for enabling a more open, interoperable ecosystem for chiplet design. Much the way Avery has helped provide comprehensive verification IP solutions for SoC and IP companies, we believe giving engineers early access to reliable verification models and testsuites will help accelerate its use and be an important factor in realizing the vision of PCIe and CXL based chiplets based on UCIe and supporting its evolution,” said Luis E. Rodriguez, verification solutions architect at Avery.

“A key to success for any standard is a broad and robust ecosystem. Avery’s experience in enabling the adoption of open standards like CXL and PCIe demonstrates commitment to delivering timely, accurate design and verification tools to help meet the market requirements. We look forward to their participation in the adoption of UCIe to make chiplet interoperability a reality,” said UCIe Chairman and Intel Senior Fellow Dr. Debendra Das Sharma.