Quadric Announces New Architecture for On-Device AI

By Tiera Oliver

Associate Editor

Embedded Computing Design

June 22, 2021


Quadric Announces New Architecture for On-Device AI

Quadric introduced a unified silicon and software platform that is designed to provide on-device AI.

Built to accelerate computation speeds while reducing power consumption, Quadric’s new general-purpose processor platform was created to meet the computing needs of  autonomous smart sensors, IoT devices, factory automation, robots, 5G infrastructure, and medical imaging. The platform is designed to handle any AI algorithm, as well as classic algorithms used for tasks such as digital signal processing, high-performance computing, and image processing.

The Quadric processor architecture is based on a hybrid data-flow and Von Neumann machine that enables high-performance on-device computing for demanding workloads including neural networks, machine learning, computer vision, and basic linear algebra subprograms (BLAS). The instruction-driven architecture enables software manageability of hardware to keep pace with on-device computing. The open software programming model is designed to provide ease of use by enabling developers to express graph-based and non-graph-based algorithms in unison.

 According to the company, Quadric’s unified platform delivers accelerator-like performance with processor-like flexibility. This integrated approach enables developers to create on-device AI applications that support decision making at the network edge.

The Quadric platform is built around the q16 processor architecture, which combines the software flexibility and programmability of a Turing complete parallel processor with a dataflow-based accelerator. Per the company, the q16 processor is the first silicon-proven instance of Quadric’s architecture for on-device AI and low-power processing of large data streams. Quadric’s first-generation q16 processor integrates a 16 x 16 array of general-purpose Vortex Cores working in parallel to process computationally demanding algorithms. The scalable quadric architecture is portable to advanced nodes down to 7 nm and 5 nm, with power consumption ranging from hundreds of mW (at 16 nm) up to 20 Watts.

To accelerate evaluation and development, Quadric offers an easy-to-use developer kit that hosts the first-generation q16 processor in a M.2 2280 (22 mm wide x 80 mm long) form factor. The developer kit supports transfer speeds up to PCIe Gen 4 x 2. The system contains 4 GB of external memory directly mapped to the q16 processor’s universal memory space. The entire M.2 system consumes a maximum of 5.5W TDP. Included with the M.2 System, the Quadric SDK enables developers to combine deep learning backbones with source-level control to build advanced AI algorithms and model algorithm performance. The processor’s data-parallel processing capabilities are exposed to the developer to provide design flexibility using Clang/LLVM.

The Quadric architecture supports all types of data-parallel algorithms through Source Mode within the SDK. Source Mode gives developers source-level C++ control of the processor’s architectural features, such as control flow, random access and optimized data-parallel execution. Examples of Source Mode kernels include GEMM, 1D and 2D N-point FFT, and image filtering. As deep neural networks (DNNs) become more complex, Source Mode also allows developers to express custom operations.

According to the company, Quadric will release an SDK update later this summer that supports no-code Graph Mode complete with support for common open-source neural networks. Graph Mode will enable developers to ingest and schedule neural networks in TensorFlow or ONNX formats. Supported neural networks will include MobileNetV2, ResNet-50, and VGG16. In addition, the new SDK release will include a TVM-based scheduler for compiling and deploying AI models.

Samples of Quadric’s first-generation q16 processor are available now in the M.2 2280 form factor. To request q16 processor samples and learn more about the Quadric platform, architecture and developer kit, visit quadric.io.

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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