Cadence Design Tool Implements ML for More Effective Digital IC Design

By Rich Nass

Executive Vice President

Embedded Computing Design

August 02, 2021


Cadence Design Tool Implements ML for More Effective Digital IC Design

When I first heard about this, it sounded like a little smoke and mirrors, to be able to work the latest buzzwords into the product’s announcement. But a deeper dive reveals that ML implementation is really taking place here.

According to the company, combining Cerebrus and Cadence’s RTL-to-signoff flow offers the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).

The list of benefits offered by Cerebrus includes:

  • reinforcement ML, which quickly finds flow solutions humans might not naturally try or explore
  • ML model reuse, which permits design learnings be automatically applied to future designs
  • improved productivity by allowing the engineer to optimize the complete RTL-to-GDS flow automatically for many blocks concurrently
  • massively distributed computing, which provides scalable on-premise or cloud-based designs, resulting in faster flow optimization

Cerebrus fits in well with the broader Cadence digital full flow, working seamlessly with the synthesis, timing, power, and verification tools for a complete design flow.

For more information,

Richard Nass’ key responsibilities include setting the direction for all aspects of OSM’s ECD portfolio, including digital, print, and live events. Previously, Nass was the Brand Director for Design News. Prior, he led the content team for UBM’s Medical Devices Group, and all custom properties and events. Nass has been in the engineering OEM industry for more than 30 years. In prior stints, he led the Content Team at EE Times,, and TechOnLine. Nass holds a BSEE degree from NJIT.

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