Tenstorrent and Imperas Set to Provide Model of RISC-V Core

By Ken Briodagh

Senior Technology Editor

Embedded Computing Design

November 03, 2023


Tenstorrent and Imperas Set to Provide Model of RISC-V Core

In a recent release, Imperas Software, a RISC-V simulation solutions company, announced that it has teamed up with Tenstorrent, an AI computing company, to make available a model of the Tenstorrent Ascalon processor core as part of the Imperas RISC-V model library.

This software simulation model, like other virtualizations, is designed to provide a functional representation of the RISC-V core as an early evaluation of firmware and drivers, and creates opportunities for debugging and analysis. The models of Tenstorrent IP that are reportedly available as part of the Imperas simulation library support many time-critical aspects of SoC development and can help address the time-to-market and time-to-volume factors for SoC developers.

"Any SoC developer that implements an IP processor core quickly discovers the fundamental interactions between the hardware and software design phases," said Simon Davidmann, CEO, Imperas Software. "Now developers using the Tenstorrent Ascalon IP can use the Imperas models as a reference for software development to support the shift-left of project schedules."

According to Tenstorrent, Ascalon is a high-performance, scalable RISC-V processor desighend for performance efficiency and to leverage its configurable core so it can better scale from the Edge to HPC data center/cloud applications. The Imperas model matches Ascalon's configuration space, the companies said, including multi and many core options, while offering fast simulation performance for software development of highly complex systems and exploration of different system architectures.

The Imperas model for Ascalon reportedly can also integrate within other standard EDA environments, including SystemC, SystemVerilog, and simulation and emulation tools from Cadence, Siemens EDA, and Synopsys. A hybrid approach is often used to combine the Imperas simulation technology with emulation environments to address interim analysis requirements while parts of the RTL of the SoC are still in development, Imperas said. 

"The Tenstorrent Ascalon processor is focused on serving the compute requirements of next-generation workloads emerging at the Edge and data center/cloud with the rapid proliferation of AI high-performance applications, including Edge AI and HPC," said Aniket Saha, VP, Product Strategy at Tenstorrent. "The Imperas model for Ascalon provides a quality model for software development and integration with many popular industry standard flows and EDA tools."

The Imperas models of the Tenstorrent IP core portfolio are available now at www.OVPworld.org. Imperas RISC-V reference models are also available via approved EDA distribution partners.

Ken Briodagh is a writer and editor with two decades of experience under his belt. He is in love with technology and if he had his druthers, he would beta test everything from shoe phones to flying cars. In previous lives, he’s been a short order cook, telemarketer, medical supply technician, mover of the bodies at a funeral home, pirate, poet, partial alliterist, parent, partner and pretender to various thrones. Most of his exploits are either exaggerated or blatantly false.

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