Product of the Week: Lattice Semiconductor’s CrossLinkU-NX Embedded Vision and Processing FPGA

By Embedded Computing Design Staff

October 02, 2023

Embedded vision and processing applications benefit from hardware that is highly configurable with versatile integrated circuits that aid in the customization of a wide range of applications. Embedded vision, sensor fusion, industrial automation, medical imaging, IoT devices, and AI and machine learning are applications and technologies that are capable of processing data and accelerating applications with the help of an FPGA.

The CrossLinkU-NX family of embedded vision and processing FPGAs from Lattice Semiconductor are ideal for automotive, communications, and consumer electronics. The solution features a low power standby mode with an Always-On (AON) consumption of < 70 uA of current under typical standby mode, supporting battery life and power consumption.

The CrossLinkU-NX FPGAs are also built on the company’s Lattice Nexus Platform for 28nm FD-SOI supporting radiation hardness, mixed-signal integration, and more for semiconductor manufacturing.

The CrossLinkU-NX FPGAs in Action

The programmable architecture is one of the most prominent highlights with the CrossLinkU-NX FPGAs featuring 17k to 39k logic cells, 24 to 56 multipliers (18 × 18) in sysDSP Blocks, 2.5 to 2.9 Mb of embedded memory (EBR, LRAM), and 36 to 192 programmable sysI/O.

The CrossLinkU-NX family features a hardened USB 2.0 operating from up to 480 Mbps, and a and USB 3.2 from up to 5 Gbps. programmable sysI/O features high performance on the bottom I/O dual rank, and wide range I/O on the left, right, and top I/O banks.

Both I/O options support VCCIO between 1.8 and 3.3 and mixed voltage support ranging from 1.0 and 3.3. The programmable sysI/O supports high-speed differential up to 1.5 Gbps and dedicated DDR3/DDR3L and LPDDR2 memory support with DQS logic, up to 1066 Mbps data rate, and 16-bit data width. The wide range I/O banks support a programmable slew rate in slow, med, and fast, controlled impedance mode, emulated LVDS, and hot socketing.

The MIPI D-PHY and D-PHY enable interfacing between devices with up to two hardened 4-lane MIPI D-PHY and additional Soft D-PHY interfaces supported by the previously mentioned sysI/O for high performance. The MIPI D-PHY supports a 20 Gbps aggregate bandwidth with 2.5 Gbps per lane and 10 Gbps per PHY, and the D-PHY supports up to 1.5 Gbps per lane. Both MIPI D-PHY and D-PHY support the CSI-2 and DSI protocols.

Getting Started with the CrossLinkU-NX FPGAs

The CrossLinkU-NX FPGAs are available in 4 mm × 4 mm to 10 mm × 10 mm package options, with an 0.8 mm pitch. The FPGA is also available with reference designs like the Lattice Propel template, host driver, and example host utilities for USB to I/O bridging and MIPI CSI-2 to USB bridging applications.

Lattice Semiconductor also provides demos of the instant on and power efficiency features of the FPGA: