Microchip’s Terabit-scale Secure Ethernet PHY Family Supports Port Aggregation for Enterprise and Cloud Interconnect

By Tiera Oliver

Associate Editor

Embedded Computing Design

September 21, 2022


Microchip’s Terabit-scale Secure Ethernet PHY Family Supports Port Aggregation for Enterprise and Cloud Interconnect

CHANDLER, Ariz., Microchip Technology announced a new family of Terabit-scale Ethernet PHYs (physical layer), the META-DX2+, designed to provide OEMs the ability to double router and switch system capacities with 112G PAM4 connectivity for 800G ports, and support for encryption and Class C/D precision timing.

The META-DX2+ is further designed to enable 1.6T (terabits per second) of line-rate end-to-end encryption and port aggregation in enterprise ethernet switches, security appliances, cloud interconnect routers, and optical transport systems.

The configurable datapath architecture of the META-DX2+ provides ShiftIO capabilities and XpandIO port aggregation for router and switch port utilization for low-rate traffic. ShiftIO, with an integrated crosspoint, provides connectivity between external switches, processors, and optics. And XpandIO is ideal in business use cases as it enables port aggregation for low-rate Ethernet clients over high-speed Ethernet interfaces.

A footprint-compatible retimer and advanced PHYs with encryption allows developers to add MACsec and IPsec to their designs on a common board design and software development kit (SDK). Similar to the META-DX2L retimer, the new META-DX2+ PHY family can be integrated with Microchip’s PolarFire® FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system.

The Ethernet PHY SDK supports META-DX2L and META-DX2+ PHY devices with API libraries and firmware, in addition to support for Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extensions, and Operating Systems (NOS) that support SAI.

“In conjunction with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs from retiming, gearboxing, to advanced PHY functionality,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, datacenter, and service provider switching and routing systems …”

Additional META-DX2+ features include:

  • Dual 800 GbE, quad 400 GbE, and 16x 100/50/25/10/1 GbE MAC/PHY
  • Integrated 1.6T MACsec/IPsec engines to offload encryption from packet processors for higher bandwidths with end-to-end security
  • More than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6T gearbox and hitless 2:1 mux modes
  • Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimize power vs. performance
  • Support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications

Additionally, the device includes IEEE 1588 Class C/D Precision Time Protocol (PTP) support for nanosecond timestamping for 5G and enterprise.

The META-DX2+ family is expected to sample during the fourth calendar quarter of 2022.

For more information about META-DX2+, visit: https://www.microchip.com/

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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