Mentor, a subsidiary of Siemens, introduced Tessent Connect, a design-for-test (DFT) automation methodology that delivers intent-driven hierarchical test implementation for IC design teams. With the release of Tessent Connect, Mentor also announced the Tessent Connect Quickstart program, offering flow assessments from Mentor’s applications and consulting services engineers.

Today’s IC designs can achieve high defect coverage for manufacturing and in-system testing by integrating dedicated on-chip infrastructure such as embedded compression, built-in self-test, and IEEE 1687 IJTAG networks. As IC designs grow in size and more of this on-chip IP is integrated, engineers have adopted hierarchical DFT approaches that break down the traditional DFT process into smaller, more manageable elements. 

With Tessent Connect, IC designers interact with the Tessent software design tools using a higher level of abstraction, which describes the intended result rather than step-by-step instructions. The benefits of this abstraction-based approach include collaboration across disparate DFT teams, plug-and-play reuse of IC components, shorter turn-around times, connectivity, and pattern generation tasks.

Mentor’s new Tessent Connect Quickstart program acts as support in delivering customized insights and services that help IC design teams fully optimize and automate their DFT processes when using Tessent Connect.

For more information about Mentor’s Tessent product line, please visit: https://www.mentor.com/products/silicon-yield/tessent/