Collaboration between RISC-V International and CHIPS Alliance Announced
April 06, 2021
News
RISC-V International and CHIPS Alliance announced a collaboration to update the OmniXtend Cache Coherency specification and protocol, along with building out developer tools for OmniXtend.
RISC-V International and CHIPS Alliance have formed a new OmniXtend working group which will focus on creating an open, cache coherent, unified memory standard for multicore compute architectures. The group will:
- Update the OmniXtend specification and protocol.
- Build out architectural simulation models.
- Reference register-transfer level (RTL) implementation.
- Create a verification workbench.
These tools for an open, standard unified memory coherency bus leveraging OmniXtend will make it easier for designers to take advantage of OmniXtend for data-centric applications.
For more information, visit riscv.org
Chad Cox is the Production Editor at Embedded Computing Design. His responsibilities are centered around content creation, writing and editing, and article research and development. Chad covers industry news and events and is known to interact with various industrial leaders via on-premise visits and online interviews. He is responsible for the digital footprint and dissemination of news via social media posts, advertising creation and the production of newsletters including the Embedded Computing Design’s Daily.
He is well versed in many facets of industrial computing including Edge AI, IoT, Processing, Security, Open Source, and more.
Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature and holds a master’s in education.
