IAR Systems and Codasip Collaborate to Enable Low-Power RISC-V-Based Applications

By Tiera Oliver

Associate Editor

Embedded Computing Design

November 30, 2021


IAR Systems and Codasip Collaborate to Enable Low-Power RISC-V-Based Applications

IAR Systems and Codasip announced their partnership enabling joint customers to build low-power embedded applications based on RISC-V. Following this, version 2.11 of IAR Embedded Workbench for RISC-V now supports the L30 and L50 processors from Codasip.

The L30 and L50 are small and energy-efficient low-power embedded processor cores from Codasip, fully customizable and adaptable to the distinct needs of a project.

IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain, providing the tools embedded developers need integrated in one single IDE. Through its optimization technology, IAR Embedded Workbench for RISC-V is designed to help developers ensure the application fits the required needs and optimizes the utilization of on-board memory.

Both Codasip and IAR Systems are participating in the RISC-V Summit 2021 which is collocated with the 58th Design Automation Conference (DAC) in San Francisco, California, on December 6-8, 2021.

More information, visit: www.iar.com/riscv or www.codasip.com.

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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