IAR Systems Extends RISC-V Solutions with 64-bit Support

By Chad Cox

Production Editor

Embedded Computing Design

March 14, 2022


Image Provided by IAR Systems

IAR Systems presented support for 64-bit RISC-V cores in the professional development toolchain IAR Embedded Workbench for RISC-V.

IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything integrated in one single IDE, including integrated code analysis tools ensuring code quality. IAR Embedded Workbench for RISC-V helps developers guarantee the application fits the necessary demands and optimize the utilization of on-board memory.

Version 3.10 of IAR Embedded Workbench for RISC-V supports RV64 RISC-V cores, including several RV64 devices from:

  • Andes
  • Codasip
  • Microchip
  • Nuclei
  • SiFive

Symmetric multicore processing (SMP) is now supported, enabling high-performance debugging of multicore RISC-V devices.

“64-bit support is an important milestone for our investment in the RISC-V technology and ecosystem,” commented Anders Holmberg, CTO, IAR Systems. “RISC-V technology adoption and interest continues to grow, especially in the Asia Pacific region, and we are committed to stay in the forefront when it comes to professional development solutions for building high-quality embedded applications across all industries.”


Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

More from Chad