Siemens Collaborates with GlobalFoundries to Provide Trusted Silicon Photonics Verification

By Tiera Oliver

Associate Editor

Embedded Computing Design

May 17, 2022


Siemens Collaborates with GlobalFoundries to Provide Trusted Silicon Photonics Verification

Siemens Digital Industries Software announced that its Calibre nmPlatform now enables designers to leverage the newest GlobalFoundries (GF) silicon photonics platform.

Per the companies, GF’s next generation, monolithic platform, GF Fotonix is the first in the industry to combine its differentiated 300mm photonics and RF-CMOS features on a silicon wafer.

The GF Fotonix process design kits (PDKs) include Siemens’ Calibre nmDRC software for design rule checking (DRC) and Calibre nmLVS software for layout vs. schematic (LVS) verification. Both Calibre tools are fully certified by GF, so mutual customers designing for the new GF Fotonix platform can continue to use the trusted Calibre nmPlatform for silicon photonic devices as they have used for previous offerings.

GF Fotonix consolidates complex processes that were previously distributed across multiple chips onto a single chip by combining a photonic system, radio frequency (RF) components, and high-performance complementary metal–oxide–semiconductor (CMOS) logic on just one silicon chip.

Silicon photonics enables companies to bring fiber optics directly into integrated circuits. However, silicon photonic devices contain curved layouts, rather than the linear Manhattan grid features found in traditional CMOS designs. Applying traditional CMOS DRC to silicon photonic layouts can yield numerous false positive errors that design teams must often spend weeks tracking down. To address this challenge, GF leverages Siemens’ Calibre eqDRC software, which allows rule checks to use equations in place of, or in addition to, linear measurements. This helps enable more accurate results, leading to fewer errors, so design teams can spend far less time and fewer resources debugging their designs.

Similarly, the curvilinear nature of photonic structures, together with the general lack of source netlists for optics, poses a challenge when performing LVS checking. Traditional IC LVS technology extracts physical measurements from well-understood electronic structures and compares them to the intended corresponding elements in the source netlist. However, with curved structures it is difficult, if not impossible, to discern where one structure begins and another ends. With the new GF Fotonix PDK with Calibre LVS, this obstacle is resolved with the use of text and marker layers to discern regions of interest.

Silicon photonic devices are often implemented in an individual die on a specific process node, then stacked and packaged with the rest of design components in multiple dies using advanced heterogeneous packaging technologies. By using the complete core Calibre offering, total verification cycle times can be greatly reduced.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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