sureCore's Ultra-Low Memory Technologies Enable Designers to Create the Reality of the Metaverse
July 11, 2022
News
SureCore's memory designs need up to 50% less power than standard, off-the-shelf memory for wearable, metaverse hardware.
One of the key challenge in designing metaverse hardware is building a power efficient frame buffer to drive the displays. These large memory subsystems can be anywhere from 10MByte to 100Mbyte in size and need to support very high data bandwidths and can present a power problem for developers. Not only is the dynamic power critical as the displays may need regular updates with video presenting the most power-hungry demands.
In addition, having such a large amount of active memory means high leakage currents which, at elevated temperatures, can dominate the power profile. Per the company, off-the-shelf memory designs from both foundries and the major IP vendors are most often optimized for area and performance with virtually no consideration for power consumption. This gives a flat, two-dimensional selection space which, rather appropriately for these three-dimensional augmented reality applications, is completely inadequate.
sureCore, as part of its bespoke custom memory development service, sureFIT, has delivered memory sub-system solutions optimized for the three-dimensional design space of Power, Performance and Area (PPA). In one AR customer engagement, sureCore was able to deliver in excess of 40% total power savings compared to off-the-shelf solutions.
Whilst a bespoke solution offers the opportunity to engineer the optimal solution for the target application, sureCore has a range of power-optimized, standard products that deliver power profiles needed by these applications. These include Everon, PowerMiser, and MiniMiser. Power savings can be realized both at nominal operating voltages and, increasingly importantly, at low to near threshold voltages allowing the application designers to tailor the power profile to the performance requirements. sureCore memories offer single rail, low voltage operation thereby allowing direct logic connection and easing system level design considerations.
For more information, visit: www.sure-core.com
Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.
She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.
Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack.
