5G Infrastructure Opens New Integration Frontiers Inside RF Chips
April 16, 2019
The 5G infrastructure now demands another round of innovation on the part of semiconductor firms to improve network efficiency with more adaptable solutions.
The advent of massive multiple-input multiple-output (mMIMO) is creating new RF challenges for base station hardware while the new radio technology facilitates the path toward 5G wireless. So, the 5G infrastructure, already facing an increasing RF complexity, now demands another round of innovation on the part of semiconductor firms to improve network efficiency with more adaptable solutions.
So far, communication equipment manufacturers are bound to create multiple cards with specific frequencies in order to meet the wireless industry requirements for a variety of licensed and unlicensed 5G bands around the world. Take Ericsson, for instance, which creates two board designs per week to keep up with all the frequency plans across the globe.
So how do we develop a single platform that is frequency-independent and can be used in multiple geographies? Especially, for mMIMO radios, which use a lot of antennas in a panel and that makes network efficiency imperative. Xilinx claims that its Zynq® UltraScale+™ RF system-on-chip (SoC) offers a single-chip adaptable platform, which can be reconfigured for several 5G standards.
Direct RF sampling
In the traditional analog approach, the RF signal chain is connected to digital front-end via JESD204 interface after RF sampling is carried out by discrete components. It also involves one or two converters per chip. Here, data conversion from one chip to another can take as much as 8 watts for transporting 320 Gb of data.
However, when you are using a lot of transmitters and receivers, as is the case in the mMIMO designs, you must be very mindful of power consumption. So, Zynq UltraScale+ offers a single-chip adaptable radio platform that carries out the direct sampling of RF signals.
Direct RF sampling processes the incoming signals directly without down conversion to the intermediate frequency (IF) signals and applies DSP techniques to perform tasks like signal conditioning in the digital domain. That eliminates the JESD204 bottlenecks when the RF circuitry goes to the next chip for tasks like network routing.
That, in turn, simplifies the analog-to-digital signal chain and allows to process a lot more data, a key advantage for mMIMO base stations in 5G systems. The single-chip adaptable platform integrates baseband, radio IP, MACs, DSP signaling and filtering, and data converters with general-purpose digital processors and a DDR4 memory subsystem.
The integration of RF data converters, for example, offer a valuable venue to reduce power consumption, footprint and bill of materials (BOM) costs. Zynq® UltraScale+ supports direct RF sampling of up to 5 Giga samples/s with 14-bit analog-to-digital converters (ADCs) and 10 G samples/s with 14-bit digital-to-analog converters (DACs).
In Zynq UltraScale+, the sample rate of RF ADC has been improved from 4 G sample/s to 5 G sample/s, and the sample rate of RF DAC has been enhanced from 6 G sample/s to 10 G sample/s. That reduces the power consumption of the RF data block by 20 percent for time division duplex (TDD) use cases. Here, it’s worth mentioning that most 5G radios are based on TDD technology.
How FPGAs empower RF design
The FPGA-centric designs typically require data converter, but until now, only low-performance converters have been integrated into FPGAs for applications like system monitoring. That’s primarily because analog and digital processors have been developed by different groups in semiconductor companies or even by different companies altogether.
The digital teams work on node migration to shrink the node size while analog engineers use older processing nodes that are stable. However, it must change in modern radio use cases like mMIMO that mandate a much higher level of integration.
Xilinx claims that Zynq UltraScale+ manufactured on a 16 nm FinFET process is a manifestation of this higher level of integration; it puts both analog and digital domains into a single piece of silicon to optimize signal flows with programmable logic.
The integration of hardware and software programmable engines eliminates discrete components, enabling up to a 50 percent reduction in power consumption and design footprint. For instance, Zynq UltraScale+ lowers the BOM cost by reducing the number of external PLL oscillators from four to one.
Besides 5G base station designs, Xilinx is also targeting this multiband radio chip at other RF applications such as phased-array radar networks and weather surveillance systems. Then, there are use cases like remote PHY nodes for cable access, lidar systems in automotive, test and measurement, and satellite communications.
Adapting to 5G world
The 5G standard is going to evolve over the next few years, and that will continue to change the system requirements. Therefore, unlike the 3G and 4G design realms, where communication equipment makers have been using ASICs, a flexible logic approach has a better chance of standing up to the incremental 5G deployments.
An ASIC solution in today’s 5G design environment could well be obsolete within a year. On the other hand, a programmable solution (Figure 3) connecting analog and digital domains can be reconfigured for a variety of 5G installations.
The article has presented the profile of a highly-integrated RF chip that carries out the process of down-converting within the digital domain and thus bypasses the traditional analog way of RF sampling that involves down conversion with discrete components.
The Gen 1 Zynq UltraScale+, made available in 2018, caters to frequency bands between 1 GHz and 4 GHz. The Gen 2 Zynq UltraScale+, going into production in June 2019, will serve bands between 4 GHz and 5 GHz, and it will support 16 x 16 MIMO configurations. Finally, Gen 3 Zynq UltraScale+, to be released in 2020, will offer direct RF support for the full 6 GHz band.