Aldec has introduced automatic UVM register generation in release 2019.04 of its Riviera-PRO verification platform. Riviera-PRO accepts CSV files or IP-XACT register description inputs, then outputs UVM register models, RTL register models, C headers, and HTML.

Riviera-PRO is able to output these files by working at the register abstraction layer (RAL) of UVM. The latest release of the advanced verification platform also contains libraries of UVM (IEE 1800.2-2107) and UVVM (2018.12.03) -compliant pre-compiled source code, documentation, and examples that accelerate test bench creation.

The tool also offers enhancements for SystemVerilog users, including the ability to create nets of integral data types (typedef), an upgraded compiler that can work with sources with longer file names, and provisions for translating VHDL packages to SystemVerilog.

Other features include upgrades to the debug suite so that toggle coverage analysis for VHDL can support logic-level transitions to and from high resistance. Support for Microsoft Visual Studio 2017 has been added as well.

For more information on Riviera-PRO visit www.aldec.com.