Solve Design Issues Utilizing ALINT-PRO
April 06, 2023
Henderson, Nevada. Aldec, renovated its linting tool ALINT-PRO to increase the support of Microchip Technology's Libero SoC Design Suite. The update allows for automatic conversion of Libero projects into ALINT-PRO’s ecosystem for static linting and clock domain crossing (CDC) evaluation of hardware devices in VHDL, Verilog, or SystemVerilog.
"FPGA designs are increasing in size and complexity requiring earlier detection of language and structural errors", said Joe Mallett, Sr. Marketing Manager at Microchip. "Designers using Libero SoC Design Suite can take advantage of Aldec's ALINT-PRO to help detect functional errors earlier in the FPGA design cycle."
Static linting helps detect a wide variety of design issues, including:
- Poor coding styles
- Improper clock and reset management
- Simulation vs. synthesis mismatches
- Incorrectly implemented finite state machines (FSM)
- Other typical source code issues throughout the design flow
To alleviate some non-deterministic concerns like data incoherence because of metastability, a CDC analysis is a must in designs with multiple asynchronous clocks.
"The use of advanced verification tools such as static linting and CDC analysis can significantly reduce the number of non-trivial bugs escaping into production, save engineering resource and more importantly, increase the reliability of FPGA and SoC FPGA designs," said Louie De Luna, Director of Marketing at Aldec. "We've had a long-standing and successful partnership with Microchip FPGA business unit since 1987 and we're happy to continue our relationship and provide value to their users."
For more information, visit aldec.com.