Boundary-scan like a pro
April 01, 2008
Boundary-scan tools enable accurate testing and high-speed in-system programming for densely packed PCBs.
Circuit access problems often arise in testing environments when designers use advanced IC packages such as ball grid arrays. Designers also constantly run into issues dealing with interconnections between memory devices and other non-boundary-scan devices.
Boundary-scan tools enable accurate testing and high-speed in-system programming for densely packed PCBs. Automated, precise fault location detection and coverage analysis reports simplify troubleshooting and allow designs to be optimized before layout.
Boundary-scan like a pro
Testing is a never-ending challenge for any designer. Devices at all levels from components to boards to systems continually evolve and become more complex, making testing even more complicated. Components like processors, I/O chipsets, and Systems-on-Chip (SoCs) have shrunk in size while gaining more functionality and increased performance levels. These types of devices adopted the JTAG boundary-scan standard for testing several years ago, but JTAG remains a difficult tool for designers to fully implement and get the best test coverage possible.
To ensure optimal test coverage, test development for interconnections between memory devices and other non-boundary-scan devices should be automated and fault diagnostics should be prepared automatically. JTAG Technologies accomplishes this with its ProVision JTAG tools. Using ProVision, a designer can quickly prepare tests and in-system programming routines and then examine and manage the details.
Based on the IEEE 1149.1 specification, these boundary-scan tools provide comprehensive coverage and simplify an embedded computing system designer‚Äôs job by identifying specific nets, components, and pins in the PCB schematic and layout. Automation combined with high levels of control and precision lets engineers maximize their designs and develop their boundary-scan applications quickly, shortening time to market.
JTAG has been around for nearly 20 years and is still evolving. Looking to the future, complex new devices will continually need better internal testing, and system-level products will want to reap the benefits of boundary scanning. New advancements in JTAG will seek to provide System-level JTAG (SJTAG) for multiboard systems and Internal JTAG (IJTAG) for IC-level testing. The IEEE standards working groups have associated test standards already in definition.
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