Imperas Announces Ratifications, Test Suites, and Functional Coverage Libraries for RISC-V

By Chad Cox

Associate Editor

Embedded Computing Design

December 19, 2022

News

Image Provided by Imperas

Oxford, United Kingdom. Imperas Software Ltd. revised its ImperasDV for maintaining the expansion of RISC-V verification supporting both RTL bug detection and analysis while collaborating with design flow implementation in EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Imperas leverages RISC-V for its ability to be customized for specific industry needs. “RISC-V offers new freedoms in design flexibility which is driving a new wave of innovation across the semiconductor industry in almost all market segments,” said Larry Lapides, VP of Sales at Imperas Software Ltd.

Verification IP – SystemVerilog Functional coverage library: riscvISACOV

Design Verification (DV) teams utilize coverage analysis as the key metric toward finalizing verification plans. The ImperasDV Verification IP extends to contain riscvISACOV, a collection of SystemVerilog source functional coverage libraries. For detailed information, visit https://github.com/riscv-verification/riscvISACOV. “Through the dedicated efforts of the specialist verification teams, with standards such as UVM and SystemVerilog, SoC verification is now a ‘solved-problem’,” said Simon Davidmann, CEO at Imperas Software Ltd.

Verification IP - Test suites

Architectural validation test suites assist RISC-V developers in making sure hardware implementations meet expectations of the software environment supporting RISC-V. The ImperasDV Verification IP has been revised to include architectural validation test suites intended for RV32E, RV64E, Zc, and Zmmul specifications. Follow the link for further information,  https://github.com/riscv-ovpsim/imperas-riscv-tests.

RVVI (RISC-V Verification Interface)

RVVI offers a general approach to key elements of the testbench to link the RTL instruction trace and reference models to utilize the ‘lock-step-compare’ verification methodology. With the RVVI, Designers have access to RISC-V specifications and features for projects that include:

  • Designs with privilege modes
  • Vector extensions,
  • Out-of-order pipelines,
  • Multi-threading
  • Multi-hart
  • Multi-issue
  • User-defined custom instructions and extensions

Davidmann continues, “As SoC developers embrace the freedoms of RISC-V, verification solutions and methodologies based on the established flows with UVM and SystemVerilog are allowing SoC DV teams to scale up to the complexities of RISC-V processor verification. ImperasDV provides the path from the established SoC techniques into the new challenges of RISC-V verification. A clear must-have for any solution is a complete design flow with full compatibility with the big 3 EDA environments to maintain the efficiency and throughput as the industry brings ever more complex designs to market without delay.”

More information on RVVI is available at https://github.com/riscv-verification/RVVI

For even more information, visit imperas.com, and watch an interview below with Rich Nass, Executive Vice President, Embedded Computing Design, and Simon Davidman.