Design management system eliminates ASIC shortcut risk

October 01, 2013

Taking shortcuts can be a risky endeavor when designing an ASIC. However, there are avenues to streamlining a design project and reducing the risk whe...


Seasoned ASIC engineers will likely tell a junior member of the project team that there are no shortcuts, especially if challenging factors come into play, for example: if the design is to be implemented on a modern, aggressive process node; or if the project team is relying on semiconductor Intellectual Property (IP) that can account for as much as 70 percent of the chip; or if the ASIC has 500 million or more gates; or if the project team delegates some or all of the design to a contract design house, relieving themselves of much of the detail but placing their trust in a separate organization. Plenty can go wrong when taking a shortcut in any of these scenarios (Figure 1).


Figure 1: Most implementation issues occur during the design phase, or are caused by issues with library files.




That does not mean, however, that there are no avenues to streamlining the design process. Ensuring project success each and every time requires the use of a design management system based on years of hands-on project management experience to ensure every project is on track and achieves its goals. Accordingly, the following focuses on the decision to devise an ASIC design management system and implement what has become an important resource for engineers and managers.

Design management system streamlines process

A design house has numerous goals when designing a chip, from achieving the highest-performance design to completing it in the shortest possible time while maintaining high quality.

ASIC designers often have more to consider than FPGA designers. For example, a large percentage of the design can be made up of third-party IP or previously implemented pieces of code. Further, process technologies are getting smaller, while gate counts continue to rise, making verification (or verifying that the ASIC works as intended) a necessity.

The goal of an ASIC design management system, then, is to provide project consistency with minimum overhead so that all designs progress in a predictable manner.

As new semiconductor process technologies evolve, each design is subjected to an ever-more-complex tool chain. One difficulty of project management, and a threat to consistency, is that each engineer will have a different idea of how the design should flow through the tools. For example, individual engineers like to automate the flow of their portions of an ASIC design through scripts that invoke tools and manage results. He or she may have a scripted routine that helps simplify output results of a detailed timing analysis. If not managed properly, this can lead to “résumé dependency” where each project is managed according to the history, skill set, and whims of the engineers. If this happens, every project is at risk if engineers join or leave the company and it becomes hard to move engineers from one project to another.

An ASIC design management system is a software-based platform that offers a standard, consistent way of doing all designs (Figure 2), balancing the needs of all projects through the use of different modules, including a data manager, a build manager, an analyzer and a monitor.


Figure 2: An ASIC design management system offers a consistent format for each design. One of these systems, for example, includes a data manager, a build manager, and an analyzer and monitor.




Files, files, and more files

During the life of a project, many files will be consumed and created, and many tools invoked with results analyzed and used to determine what to do next. A design management system automates and manages this process by providing a consistent methodology and flow throughout the chip implementation process.

It’s easy for things to go awry in ASIC design and tempting to place faith in prior work that has been done by someone else. Proceeding without checking everything, from scripts to code to library files can produce problems that can result in rework.

The wide variety of library files is a good example, especially if third-party IP is used with numerous files reflecting different process variants and corners. Even with established processes, it is not unusual to find a software bug in those files, and there’s a real risk that such a bug might not be found until late in the project. With so many variants of library files and data, it is easy to mistakenly use the wrong one and, thus, the need for a way to manage revision control.

Typically, these library files are managed manually by copying from an original location into the data structure for the project, an error-prone effort. File names or directory names might indicate which files, yet those names may have no bearing on what’s inside the file, and may actually be wrong. This is where a design management system can help by automatically locating, reviewing, and storing all of the project’s input files. It parses (analyzes, organizes, and distributes) the files’ contents to ensure that mistakes can’t happen. It enforces a standard file structure so potential problems can be discovered early in the design phase, not later when they might impact schedule and costs.

Automated analysis plays a critical role in early reviews of the design. All of the design and IP files are scanned to extract the hierarchy, trace the clocks, and inspect module connectivity. Information from these early analyses help design engineers focus their efforts on the more problematic areas of the design.

Automatic optimization

Once the pre-design analysis is complete, work on the design can proceed. The build manager and analyzer modules are important components of this phase. The build manager encapsulates the entire ASIC flow, ensuring that every project has the same structure. Individual engineers don’t maintain their own build scripts. Instead, the design management system automatically generates build scripts (sets of programmatic instructions) and creates working directories for all of the various files needed by the EDA tools used for designing the ASIC.

ASIC design is not a linear process, and it might not be obvious which of the many design strategies might be the most effective. The build manager creates and runs a series of different design options so the project team can review them and find the best solution.

The analyzer, meanwhile, performs results aggregation and optimization (Figure 3). The various electronic design tools that range from synthesis and simulation to verification and test will generate a large number of different results files that, for a human, are not easy to read, making it hard to identify the most pressing problems. The analyzer extracts results from the files and summarizes them in one place, making it easier to review the state of the current build.


Figure 3: The analyzer module extracts results from files and summarizes them in one place.




Implementing the ASIC top level

With a design management system, individual blocks in an ASIC design can be straightforward to implement. Each engineer is assigned a piece of real estate from the floorplan, and place and route within that area can proceed uneventfully, assuming there is enough silicon area to work in. It takes additional logic and interconnect to tie the blocks into a single design at the top level, which can be challenging.

When designing the floorplan, it is critical to leave area for the top-level ASIC integration to ensure the top-level logic (components) can fit into the channels. These added components must be stuffed into the channels provided around and through the finished blocks.

Depending on the size and complexity, a chip design project may involve a handful to dozens of engineers, all working on different blocks at the same time. The project manager will want visibility into how different aspects of the project are coming along.

As its name suggests, the monitor module has constant visibility into the current state of each design activity. Since it works in the background, it gives management visibility into progress without disturbing and slowing the design work. Any identifiable issues will be visible. Because they’re caught early, they can be fixed early, making schedule slips less likely as the project progresses.

Getting to the finish line

Tapeout is the most critical time in the project and where any final changes to the design must be addressed. These include ECOs (changes to the netlist) and DCOs (changes to the RTL code) (see Figure 4). In the ideal world, all changes to the design would be in place before tapeout. In reality, it is an expected part of the design process that final design changes will be identified and must be addressed before the final tapeout.

A design management system should be able to accommodate last-minute changes and incorporate them into the design without having to go back and start over. Since the design management system has direct access to all project data, it can quickly accept design changes and automatically rerun the design with the new data.


Figure 4: A design management system can accommodate last-minute changes and incorporate them into the design.




Winning the high-stakes ASIC design game

The stakes in ASIC design are enormous and range from lost market opportunities and revenue to a company going out of business as a result of a design failure. Too many things can go wrong when taking the risk of shortcuts. By establishing a standard project process and structure, a project team can engage each new project with confidence that it will proceed in a predictable, orderly fashion – a much better option than taking shortcuts. That process should include the implementation of a design management system. Uniquify, for example, has developed and implemented Perseus, a design management system that forms a project’s backbone. Such design management systems are a critical resource for designers and managers.

Bob Smith is Senior Vice President of Marketing and Business Development at Uniquify. He began his career in high tech as an analog design engineer working at Hewlett Packard. He has spent more than 30 years in various roles in marketing, business development, and executive management primarily working with startup and early-stage companies. He received a Bachelor of Science degree in Electrical Engineering from U.C. Davis and a Master of Science degree in Electrical Engineering from Stanford University.


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