Microsemi's PolarFire FPGAs Add a Low-Power Checkbox to the Mid-Range Density

By Rich Nass

Executive Vice President

Embedded Computing Design

February 22, 2017


We just concluded our Annual Embedded Market Study, where we asked people like you, our reader community, questions about their design habits, choices, and product selections.

In one question, we asked readers to choose the FPGAs that they’re working with. Inevitably, Xilinx comes up as number one, and Altera is number two. But there’s a new competitor entering the fray, with a recent announcement that could alter that landscape.

Microsemi, a company that’s not new to the FPGA scene, is making significant strides, as our study shows. And the release of its PolarFire architecture could move them much higher in the mix when we conduct next year’s study, generally done near the end of the year. According to Microsemi, PolarFire fits into a new category of cost-optimized, yet high-performance non-volatile (NV) flash FPGAs. It also adds low power to the mix, potentially really low power for the category that it serves, lower to mid-range densities.

PolarFire, manufactured on a 28-nm Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) NV process on standard CMOS, is aimed at the communications, defense, and industrial sectors, including the growing Industrial IoT or Industry 4.0 market. Unlike typical SRAM FPGAs, the NV flash devices deliver 500,000 logic elements and 12.7 Gbit/s serializer/deserializer (SerDes) transceivers at what he company claims is up to 50% less power than the competition, thanks to a Flash*Freeze mode. In less than 100 μs, Flash*Freeze places the FPGA fabric in a low-power quiescent state, and the state of the memory and flip-flops are preserved while in this state. Exit from Flash*Freeze to I/Os typically occurs in under 200 μs.

In collaboration with IP provider Silicon Creations, Microsemi developed the transceivers for maximum efficiency, resulting in a total power of less than 90 mW at 10 Gbits/s. Combine that with a static power consumption of 25 mW at 100,000 logic elements, zero inrush current, and the Flash*Freeze mode, you get a standby power specification of 130 mW at 25°C. Microsemi also offers a power estimator to analyze a design’s power consumption. After implementation, the SmartPower Analyzer can be used to access full-design power.

Knowing that security is paramount in most of the aforementioned applications, the PolarFire family leverages security technology from Cryptography Research Inc. (CRI), now a Rambus company. That includes differential power analysis bit-stream protection, an integrated physically unclonable function, 56 kbytes of secure embedded NV memory, built-in tamper detectors and countermeasures, and true random number generators.

The PolarFire FPGA product family is currently shipping to early access customers. Samples for general availability will be offered in the second quarter. Development can be done using Microsemi’s Libero SoC Design Suite, which includes Synopsys Synplify Pro synthesis, Mentor Graphics ModelSim Pro mixed-language simulation, and Microsemi’s differentiated FPGA debugging tools.

Richard Nass’ key responsibilities include setting the direction for all aspects of OSM’s ECD portfolio, including digital, print, and live events. Previously, Nass was the Brand Director for Design News. Prior, he led the content team for UBM’s Medical Devices Group, and all custom properties and events. Nass has been in the engineering OEM industry for more than 30 years. In prior stints, he led the Content Team at EE Times, Embedded.com, and TechOnLine. Nass holds a BSEE degree from NJIT.

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