Siemens Extends Support of Multiple IC Design Solutions for Samsung Foundry’s Latest Process Technologies
November 29, 2021
Siemens Digital Industries Software announced it has enabled several of its electronic design automation (EDA) product families for the latest versions of Samsung Foundry’s advanced processes, including Siemens’ solutions targeting advanced packaging, electrostatic discharge (ESD) rules, and integrated circuit (IC) design in the cloud.
Per the company, Samsung has successfully evaluated Siemens’ digitally integrated High Density Advanced Packaging (HDAP) flow for the foundry’s MDI (multi-die-integration) packaging process. For customers, this optimization helps enable seamless integration across multiple dies through construction of the complete MDI package assembly.
The Siemens tools evaluated by Samsung for the foundry’s advanced packaging technology include:
- The Xpedition Substrate Integrator software, which Samsung used to generate a top-level “golden” system netlist for 3D LVS verification with Calibre 3DSTACK software. This netlist delivers foundry qualified sign-off MDI heterogeneous 3.5D structures.
- Xpedition Package Designer, which Samsung evaluated for physical implementations of its 3.5D Silicon Interposer, is a first for a package design tool targeting Samsung’s MDI technology, and it enables early-stage PSI (power and signal integrity) analysis in connection with Siemens’ HYPERLYNX suite of tools.
- HYPERLYNX, which supports PSI analysis of SerDes and HBM (high bandwidth memory) channels implemented on Samsung’s 3.5D Silicon Interposer.
- The Calibre xACT 3D software and Calibre xL parasitic extraction tools extract RCLK parasitics in highly complex 2.5D and 3D packaging configurations. The Calibre parasitic extraction tools help enable signal integrity-aware analysis of the entire HBM channel implemented on the 3.5D Silicon Interposers.
Verification for design compliance with foundry electrostatic discharge (ESD) rules is a critical step in the design tape out process. The number of checks required, combined with the sheer volume of design data for full chip simulation at advanced technology nodes, demands a robust physical reliability platform.
According to the company, Siemens’ Calibre PERC software’s advanced algorithm development functionality, parallel compute capabilities, and automated context-aware architecture have created a paradigm shift in analysis methodology. These developments have cut the runtime of full chip ESD verification by half while maintaining accuracy, improving verification quality, increasing checking coverage, and allowing for suitable speed in new kit development.
Working closely with Samsung, Siemens developed a flow capable of being automated from a single configuration file. This flow can generate verification kits for different technologies and with minimal development effort. Samsung Foundry is the first foundry globally to leverage the parallel compute capabilities of Calibre PERC in their ESD checking solution. All of these have resulted in improved runtimes, reliability, and maintainability for Samsung’s advanced full chip PERC analysis kits.
Siemens and Samsung have also developed best practices for design teams looking to leverage cloud scaling for faster physical verification run times. These best practices include setting up batch Calibre nmDRC runtimes, in addition to other Calibre products that design teams might choose to run, such as Calibre SmartFill software, once they have placed their design on the cloud.
For more information, visit: www.samsungfoundry.com