NXP Develops Dual-Core GHz Crossover MCU for Edge ML

By Laura Dolan

Senior Copywriter


October 03, 2019


NXP Develops Dual-Core GHz Crossover MCU for Edge ML

New dual-core Arm Cortex-M based crossover microcontroller (MCU) breaks gigahertz (GHz) barrier and accelerates advanced Machine Learning (ML) applications at the edge.

NXP has released the i.MX RT1170 crossover family, the first MCUs in the industry capable of running at up to 1 GHz. The devices are based on a dual-core Arm Cortex-M architecture, featuring an -M7 core able to run at 1 GHz and -M4 core that runs at 400 MHz. These are accompanied by a 2D pixel-processing vector graphics engine and NXP EdgeLock security.

The dual-core processor architecture is capable of running machine learning (ML) applications like facial recognition and natural language processing in parallel.

With 2974 DMIPS of performance and a 6468 CoreMark score, the i.MX RT1170 relies on a tightly-coupled memory (TCM) architecture to achieve 12 ns interrupt response times when executing from 2 MB of on-chip SRAM. 512 KB of that can be configured as ECC SRAM for the Cortex-M7, while 256 KB can be allocated as ECC SRAM for use by the Cortex-M4.

According to NXP, the TCM architecture allows ML inferencing tasks to be executed on the i.MX RT1170 Cortex-M7 core approximately 5x faster than the fastest competing MCU on the market. The 2D vector graphics core can also be of assistance in such workloads thanks to support for the Open VG 1.1 API, helping offload graphics-intensive workloads from the -M7 core.

Built on a 28 nm FD-SOI process, the MCUs are the also first to reach this technology node plateau. This helps optimize the chips in terms of both active and leakage power, and complements the independent power domain architecture that permits developers to completely power down one core or the other when not in use.

The EdgeLock 400A security subsystem provides tamper detection, secure boot, secure key storage, an SRAM PUF, and crypto accelerators for AES, ECC, RSA, and SHA algorithms. An in-line encryption engine (IEE) and on-the-fly decryption (OTFAD) engine also enables line-rate processing of data stored in both internal and external memories. The IEE operates on SRAM and DRAM, with the OTFAD running on external serial and parallel flash memory.

The devices can be programmed using NXP’s MCUXpresso SDK and the eIQ machine learning software development environment. eIQ is integrated into the Yocto BSP and MCUXpresso SDK.

Interested parties can learn more by visiting www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i.mx-rt-series/i.mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170 or stopping by the NXP booth at Arm TechCon 2019.