Renesas’ ClockMatrix System Synchronizer Utilized in AMD's Zynq® UltraScale+™ RFSoC DFE ZCU670 Evaluation Kit, Reference Design for 5G New Radio
September 30, 2022
News
TOKYO-- Renesas Electronics Corporation announced that its 8A34001 System Synchronizer for IEEE 1588 has been integrated in the AMD Zynq® UltraScale+™ RFSoC DFE ZCU670 Evaluation Kit and reference design for 5G New Radio (5G NR).
The AMD ZCU670 is an evaluation and development platform based on Zynq UltraScale+ RFSoC DFE, the latest AMD silicon for 5G NR for FR1 and FR2 (mmWave) O-RAN applications. The solution will be made available as part of the AMD O-RAN reference design where it is used to implement the S-plane functionality in an O-RU reference design.
Renesas’ ClockMatrix™ Family of high-performance, precision timing solutions are designed to simplify clock designs for high-speed applications with ultra-low jitter and precision timing signals based on the IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE).
Renesas also offers open-source SYNCE4L and PCM4L, built on open source PTP4L, and device drivers in a Linux kernel for the 8A34001.
The 8A34001is designed to exceed next-generation 5G radio requirements, including synchronization, with full ITU-T G.8273.2 T-BC/T-TSC class C and D compliance.
According to the company, the 8A34001 performance has been verified on the ZCU670 evaluation platform and shown to exceed the 5G system requirements. The relevant compliance reports and test results are available from Renesas upon request.“Our close collaboration with Renesas provides the key functionality for our O-RU reference designs,” said Brendan Farley, Corporate Vice President of Wireless Engineering at AMD.
The AMD Zynq UltraScale+ RFSoC DFE ZCU670 Evaluation Kit is available today for qualified customers. Visit www.xilinx.com/products/boards-and-kits/zcu670.html for more information.
The entire ClockMatrix family of timing devices is available from Renesas and its authorized distributors. More information is available at www.renesas.com/ClockMatrix.
For more information, visit: www.renesas.com/clocks
Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.
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Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack.
