Breker Verification Systems unveils Trek5 with fully compliant support for Accellera Portable Stimulus Standard

June 12, 2018


Breker Verification Systems unveils Trek5 with fully compliant support for Accellera Portable Stimulus Standard

Trek5 portfolio leverages "Intelligent Testbench," techniques to synthesize complex test cases for UVM and SoC verification.

Breker Verification Systems, the leading provider of Portable Stimulus-compliant software, today unveiled the latest version of its Trek portfolio and announced full compliance with release 1.0 of the Portable Stimulus Specification (PSS) from Accellera.

The Trek5 portfolio leverages innovative testbench and test synthesis technology to accelerate and simplify complex test case generation for universal verification methodology (UVM) and system-on-chip (SoC) verification flows. The tool suite, including TrekSoC, TrekUVM, TrekSoC-Si and several “TrekApps,” will be demonstrated in Breker’s Design Automation Conference (DAC) Booth #1419 June 25-27 at the Moscone Center West in San Francisco.

Trek5’s scenario modeling methods offer full and complete support for Accellera PSS version 1.0 Domain Specific Language (DSL), as well as the PSS C++ Format. It also includes support for an extended native C++ mode and is backward compatible from previous formats.

Unique model configuration capabilities with scenario path constraints provide high-level configuration of graph-based models, a full hardware/software interface (HSI) layer and enhanced procedural modeling options over the base PSS declarative capability. New test synthesis technology is included in the new product suite with advanced solver engines, test case scheduling and synchronization engines, UVM and SoC deployment optimizers, memory management and system services modules.

Several more advances add a new visual editor GUI that allows scenario models to be drawn as graphs automatically generating PSS code, along with an updated test map and graph viewers that display synchronized multi-threaded UVM or C tests. Trek5 offers enhanced Cache Coherency, Power Domain and ARMv8 Verification “TrekApps,” along with full support for and integration with third-party simulators, emulators and debug environments such as Synopsys’ Verdi.

The Trek5 portfolio is shipping now on a limited production basis. Pricing is available upon request.

Breker’s Chief Marketing Officer David Kelf will present “Practical Applications of Portable Stimulus” during Verification Futures (VF2018) Thursday, June 14. The talk will explain how industry leaders such as Broadcom, IBM and Cavium are using Breker’s Trek in practical applications to improve UVM, SoC and silicon bring-up verification. Kelf will discuss how PSS can be used across the verification process. VF2018 will be held in Reading, U.K., and online.

In 2008, Breker first introduced a graph-based approach for test case synthesis that formed the basis of the Accellera Portable Stimulus Standard. Breker’s Trek product suite and apps gives chip design verification groups true Verification GPS (Graph-based, Portable, Shareable) with its Portable Stimulus solutions. The easy-to-understand Graph-based intent specification provides Portability across verification platforms, scaling from intellectual property (IP) to system on chip (SoC) for vertical reuse and enabling horizontal reuse across simulation, emulation, prototyping and final silicon. It is Shareable across global diverse teams, project revisions and communication channels.

TrekSoC and TrekUVM are in use at large and mid-sized semiconductor companies worldwide on a variety of projects. Using an Intelligent Testbench approach, the tools synthesize PSS scenario models to create advanced test case sets that can be deployed into existing UVM and SoC verification environments. This provides UVM multi-threaded tests without the authoring headache, and software-driven plus transactional SoC tests that fully prove complex operation scenarios such as cache coherency. Multiple deployment models provide easy insertion of the test sets, plus generated scoreboards and coverage models, into existing testbenches across the entire verification process, allowing for direct debug and coverage analysis of operational scenarios. Applications range from servers, networking, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to mobile and base stations for cellular wireless.

As a founding member and an active participant of the Accellera Portable Stimulus Working Group (PSWG), Breker contributed a working C++ language representation for the standardization efforts. As a result, users have access to an eventual standard based on practical and proven verification expertise and years of experience.