PLS' UDE Enables Multicore Debugging and Trace for New NXP S32Z and S32E Real-Time Processors

By Tiera Oliver

Associate Editor

Embedded Computing Design

July 18, 2022


PLS' UDE Enables Multicore Debugging and Trace for New NXP S32Z and S32E Real-Time Processors

With the new version UDE 2022 of the Universal Debug Engine, PLS Programmierbare Logik & Systeme introduces the multicore debug and trace support for the new NXP Semiconductors S32Z and S32E real-time processors. 

The NXP S32Z and S32E real-time processors are designed to extend NXP’s S32 Automotive Platform and target new consolidated domain and zonal vehicle architectures. Designed to provide the real-time behavior of microcontrollers, but with a combination of gigahertz speed, safe multi-app integration, and memory expansion capabilities, the devices target propulsion domain control, electrification, and safety applications.

The S32Z2 and S32E2 series devices are manufactured in 16 nm technology and combine eight Arm Cortex-R52 cores, running at 600 MHz to 1 GHz, with Cortex-M33 cores for special purposes like system management and communications. For advanced timer functions to be realized in real-time applications, a clustered Generic Timer IP Module (GTM v4.1) is implemented. A network-on-chip (NoC) ensures communication between the main core clusters and other functional blocks. Depending on the device, up to 64 MB integrated flash memory is available. The non-volatile memory can be extended with external QuadSPI NOR, eMMC, or SDHC NAND memories, as well as with LPDDR4 flash memory supporting large applications and data.

With its user-friendly and intuitive UDE debugger platform, PLS gives developers access to the S32Z2 and S32E2 devices. The main Cortex-R52 processor cores, the Cortex-M33 system management and communication cores as well as the GTM are all visible and can be controlled within one common debugger instance. Per the company, there is no need to open separate debugger instances for the different core architectures. The UDE allows debugging of C/C++as well as assembly code for the Cortex-based cores including the Arm and Thumb-2 instruction set. Debugging of the Multi Channel Sequencer (MCS) of the GTM can be conducted on assembler as well as C code level. The UDE supports GTM-C compilers from various compiler vendors. 

The MemTool add-on, which is an integral component of UDE, as it provides functions that enable programming of the integrated flash memory as well as the external QuadSPI NOR, eMMC, and SDHC NAND memories and offers also support for OCOTP (On Chip One-Time Programming). 

By using the multicore run-control management, UDE allows developers to control the cores of the S32Z2 and S32E2 processors using traditional run-mode debugging, i.e. with breakpoints or single-stepping, either all together, in groups, or individually. All cores in such a run-control group can be started and stopped almost synchronously. This helps to keep a consistent state of the respective application during debugging. Multicore breakpoints are also designed to simplify the debugging of complex applications, especially in shared code. A multicore breakpoint is effective, no matter which core is currently executing the specific code.

With UDE 2022, the debugging capabilities for MCS channel code of the GTM have been extended to include breakpoints and single stepping. These features relay on new hardware debug functions that are available with the GTM v4.1, which is integrated in the NXP S32Z and S32E real-time processors. 

For non-invasive debugging and runtime analyses of multicore applications, UDE provides extensive functions based on recorded trace information from the device’s Arm CoreSight trace system. This allows both the program flow and data transfers to be recorded. UDE provides comprehensive configuration options for the ETMv4 of the Cortex-R52 cores as well as the ETM-M33 of the Cortex-M33 cores in order to filter for example the trace data to be recorded. In addition to the core trace, the transactions via the NoC can also be observed by the trace system and investigated with UDE. For this, too, the UDE offers configuration options for filtering the data. The trace support for the GTM, including program trace for the MCS channel programs as well trace of GTM signals, is in preparation. 

For recording the trace data, either the UAD2next or the UAD3+ from the PLS’ Universal Access Device family can be used. To store trace data, the UAD2next features 512 MB of trace memory and the UAD3+ up to 8 GB. The fast download of the trace data from the chip towards the UDE is done via the High SpeedSerial Trace Port (HSSTP) of the S32Z2 and S32E2 processors.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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