SEGGER and Cadence Add Native J-Link Support for Cadence Tensilica Cores

By Tiera Oliver

Associate Editor

Embedded Computing Design

October 10, 2022


SEGGER and Cadence Add Native J-Link Support for Cadence Tensilica Cores

Monheim am Rhein, Germany – October 10th, 2022 – SEGGER announced native J-Link debug probe support for select use cases with the Cadence Tensilica Processor IP. The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1), and also the Tensilica Fusion F1 DSP.

SEGGER also announced high-speed download and debugging support for the latest hardware versions of all commercial SEGGER J-Link models (J-Link BASE, J-Link PLUS, J-Link ULTRA+, and J-Link PRO) via JTAG and SWD.

“The drive to push intelligence further out to the edge means that more and more MCUs and SoCs contain our Tensilica CPU and DSP IP,” said George Wall, Group Director of Product Marketing for Tensilica Xtensa Processor IP at Cadence. “The new SEGGER implementation enables us to use the J-Link GDB Server as a native J-Link driver in our Tensilica Xplorer Integrated Development Environment (IDE), resulting in a significant performance increase. As a result, customers will be able to debug their firmware running on Tensilica cores more quickly.”

The Cadence Tensilica core support has been added to the J-Link software pack and is available for download on the SEGGER website.

For more information on J-Link, please visit:

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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