SmartDV Heads to DVCon Europe to Showcase VIP Support for Verilator and TileLink, Demonstrate Smart ViPDebug Protocol Debugger
November 05, 2019
Smart ViPDebug Demo will Highlight Ability to Reduce Debug Time through Linked Waveform, Transaction Database Views.
WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification, Design IP, custom VIP and Design IP development, RISC-V verification services
WHAT: Will highlight its range of VIP at DVCon Europe (Booth #404) and demonstrate its Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations. It will profile its VIP support for Verilator, the free, open-source hardware description language (HDL) simulator. Also showcased will be TileLink VIP to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs.
WHEN: Tuesday, October 29, and Wednesday, October 30
WHERE: Holiday Inn Munich City Centre, Munich, Germany
Attendees can schedule meetings to discuss SmartDV's support for Verilator and TileLink or arrange for private demos at [email protected] to learn more about Smart ViPDebug.