Solid Sands' SuperTest to Help SiFive Advance RISC-V

By Tiera Oliver

Associate Editor

Embedded Computing Design

January 31, 2022


Solid Sands' SuperTest to Help SiFive Advance RISC-V

SiFive is currently building a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development.

These new developments include compiler algorithms, build system integration, and new Verilog RTL generation techniques. SiFive needed a compiler test and verification tool, not only to verify the functionality of its existing compiler offering, but also to help develop its new IDE infrastructure. The tool SiFive chose was Solid Sands' SuperTest.

SiFive currently uses SuperTest for verification and testing of the GCC and LLVM compilers and libraries it supplies with its IDE, as well as for regression and release testing. Over the two years the company has been using it, SuperTest has helped to identify several previously unknown code generation errors in both compiler systems.

SiFive is also the provider of RISC-V IP and one of the contributors at RISC-V International, the non-profit organization that supports the free and open RISC-V instruction set architecture and extensions. The attractions of RISC-V are two-fold. Firstly, the ISA is license free, removing the cost barrier for adoption by commercial, research, or academic users. Secondly, the architecture is modular, extensible, and customizable, allowing the addition of application-specific instructions and hardware acceleration features at the architecture level, while also leveraging the benefits of industry-wide development of ratified standards for extensions.

For example, SiFive has recently introduced its SiFive Intelligence X280, which extends RISC-V with SiFive Intelligence Extensions that integrate dedicated AI acceleration technology and extended data type support into the RISC-V instruction set architecture. With comprehensive support for TensorFlow Lite, the result is a programmable, scalable, and configurable platform to meet modern AI/ML processing requirements from the edge to the cloud, providing out-of-the-box compatibility with a wide range of machine learning models. 

Because adding application-specific instructions has implications for the compiler and potentially also the libraries, similar enhanced RISC-V architecture developers may want to take advantage of SuperTest’s comprehensive verification capabilities, such as its CGTrainer code generator trainer, which provides a systematic way of testing a modified compiler’s back-end. In such situations, SuperTest also provides a way of checking that the basic functionality of the compiler − its correct implementation of the C or C++ language specification − is not broken by the addition of these new instructions.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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