Codasip Announces First Commercial Implementation of CHERI Memory Protection

By Ken Briodagh

Senior Technology Editor

Embedded Computing Design

October 31, 2023


Codasip Announces First Commercial Implementation of CHERI Memory Protection

RISC-V is growing rapidly in adoption and attention and leading up to the RISC-V Summit, taking place in Santa Clara November 7 and 8, Codasip has introduced its 700 family of RISC-V baseline processors, designed for custom embedded solutions of all types, and it’s also announced the industry’s first commercial implementation of the Capability Hardware Enhanced RISC Instructions (CHERI) security technology for RISC-V.

CHERI was developed at the University of Cambridge, and the technology has been shown to be quite reliable in experimental processors. Now, according to the release, it will for the first time be available in a commercial offering. Codasip said its goal for the CHERI implementation is to offer secure-by-design products that enable preventive security measures without relying on patches from outside vendors.

(Editor’s note: Embedded Computing Design staff will be on-site at the RISC-V Summit, so find us and say hi, and make sure you come back here for live coverage!)

Codasip’s new custom compute product line, or family, is reportedly includes application and embedded cores, and is designed to complement the company’s existing cores by offering a different starting point to fit needs for higher performance. The first core in the family is the A730, a 64-bit RISC-V application core, now available to early-access customers, and Codasip Studio allows users to optimize each baseline core for target use cases, according to the release.

This new 700 family makes its processors available in standard configurations for quick start, but the real power, Codasip says, is in the customizability. Using the company’s Codasip Studio, developers can enable different levels of processor optimization for each use case through advanced profiling, which can reportedly improve results and shorten time-to-market.

“The great part is that you can target all sorts of performance parameters,” said Brett Cline, COO at Codasip. “It’s about customer-driven development. If the software manager and the hardware manager and work together, that’s great.”

The CHERI news is particularly of note because it’s targeted at memory safety and data protection. Cyberattacks are a constant concern and, according to the Common Vulnerabilities and Exposures (CVE) Program, about 70 percent of OS and browser vulnerabilities it has documented in the last two decades can be attributed to software memory errors.

“Heartbleed would have been preventable,” Cline said, if CHERI had been in place at the time. “Security is everyone’s responsibility,” he added. “You have to build it in. Attack as early in the flow as you can.”

Codasip will be participating at the RISC-V Summit in Santa Clara, California, on November 7-8. The company will showcase its solutions and present a keynote and several technical topics.


Ken Briodagh is a writer and editor with two decades of experience under his belt. He is in love with technology and if he had his druthers, he would beta test everything from shoe phones to flying cars. In previous lives, he’s been a short order cook, telemarketer, medical supply technician, mover of the bodies at a funeral home, pirate, poet, partial alliterist, parent, partner and pretender to various thrones. Most of his exploits are either exaggerated or blatantly false.

More from Ken