Is RISC-V Worth the Risk? The Tools & Partners You Need to Know

By Ken Briodagh

Senior Technology Editor

Embedded Computing Design

August 16, 2023


Is RISC-V Worth the Risk? The Tools & Partners You Need to Know
Tools and Partners in RISC-V

RISC-V is the hot, new thing on the Embedded Block, with nearly every industry talking about adopting, switching, or running pilot programs. But it’s unclear whether this decade-old architecture is delivering on all this hype as of yet. RISC-V was conceived about 15 years ago and first released about 10 years ago. Don’t think it’s untested tech, however.

“It’s matured quite a bit since then,” Tim Morin, Technical Fellow, Microchip Technology, told us. “If they’re offering RISC-V cores in the market, you know you’re getting IP that’s qualified and has staying power.”

RISC-V ISA is most often positioned as an open source competitor to ISAs configured with ARM IP or architectures, especially in the consumer and IoT, military, telecommunications, AI and ML, and Edge computing industries, and recently it looks like it’s moving into automotive and the data center and server spaces.  Many of the microprocessors and microcontrollers based on Arm IP and those from the RISC-V community are built to handle many of the same kinds of tasks, so they have more in common than differences and the major contrast drawn between them is the costly licensing fees Arm charges that don’t apply to the open ISA offered with RISC-V.  With that said, Arm does not yet appear to be losing much market share to RISC-V implementations. I’m not saying that you can get RISC-V silicon for free, but a large burden is removed from the supplier.

One of the strengths of RISC-V that’s giving it some of this staying power is flexibility. “The really interesting thing about RISC-V is that people can use it like a traditional microcontroller,” said Shawn Prestridge, US FAE team leader, IAR Systems. “However, you can also customize the chip so those who are FPGA-minded can add extra instructions to the RISC-V core or put in another ASIC for their project.”

With all that background in mind, let’s take a look at some of the key tools that are important to development in the RISC-V ISA ecosystem.

RISC-V Tools to Know

If you’ve never worked with RISC-V, or you’re just getting started, there are a few key tools with which you should begin getting familiar. But before getting into the more granular stuff, one bit of advice to begin with: find some reliable quick start guides and scripts, especially while you’re learning, playing around and even building your first test implementations. The ground here is well-tilled and who’s got the time to build entirely from scratch? Also, I’m going to skip describing a few basic things that aren’t specific to RISC-V, but you will need: compilers and libraries, boot loaders and monitors, OS and OS kernels, verification tools, and the UI/UX.

With that in mind, you can find excellent examples of many of the tools we’re about to talk about below on GitHub, so check that out after you’re done here. RISC-V International also offers a full tool listing (from amongst its membership) here. What follows is a list of the some of the key tools and tool sets you’ll need to consider for RISC-V implementations.


Like with any hardware-software project, load up your favorite system hardware sim platform so you can validate, profile, and debug as you model, build and before you launch.

Spike is designed to implement a functional model of one or more RISC-V harts, or hardware threads. It supports RV32I, RV64I, RV32E, and RV64E base ISAs, and several extensions, including Zifencei and Zicsr, and cryptography extensions in the Zk, Zkn, and Zks groups. It conforms to both RVWMO and RVTSO, and includes Machine, Supervisor, and User modes, along with versioning and API extensions. You should note that the C++ interface to Spike's internals is not considered a public API, and backwards-incompatible changes will be made without incrementing the major version number.

RISC-V based Virtual Prototype (VP) is an open tool supported by the German Federal Ministry of Education and Research and by the University of Bremen graduate school SyDe. It includes RV32GC and RV64GC core support, has software debug capabilities with Eclipse, and a virtual Breadboard GUI with C++ and Lua modeled digital devices. VP offers FreeRTOS, RIOT, Zephyr, and Linux support and also supports simulation of multi-core platforms. In order to test the software examples, a configured RISC-V GNU toolchain is required in your $PATH.


If you’re going to be running at least one virtual machine as part of your RISC-V setup, you’ll want a hypervisor to run these systems. Xvisor is a type-1 bare metal monolithic hypervisor designed to be light-weight, portable, and flexible. Its source code is designed to be portable to most general-purpose 32-bit or 64-bit architectures as long as they have a paged memory management unit (PMMU) and a port of the GNU C compiler (GCC).

RVirt is an S-mode trap-and-emulate hypervisor for RISC-V. It is built for QEMU's virtual machine type, but partially supports the HiFive Unleashed, according to the GitHub summary. It can run multiple instances of Linux as guest operating systems and can run either on the Berkeley Boot Loader or with its own M-mode stub. The makers say the latter is much faster. What's most interesting about RVirt is that, while many RISC-V hypervisors, including Xvisor, must run on processors that have hardware virtualization extensions like Intel VT-x or RISC-V's planned H-extension, RVirt doesn't need the additional layers and can run on any sufficiently powerful 64-bit RISC-V processor with an MMU.

PPA Measurement

Whenever you’re building an ISA or SoC, you’re looking at and controlling for PPA. RISC-V International, which administers RISC-V standards, has redefined PPA for RISC-V specifically as follows: “P = relative power in terms of memory (code + data) access rates; P = relative performance in terms of execution cycles and dynamic instruction path; A = relative static code size.” Again, there are many tools on the market for this, but one of the leading options comes from Synopsys.

Synopsys RTL Architect is designed with a fast, multi-dimensional implementation engine that can predict the power, performance, area, and congestion impact of RTL changes. It's built on a unified data model and leverages Synopsys implementation and golden signoff solutions to deliver accurate results with the end goal of reducing development time with better outcomes.

Codasip Studio takes a distinctly customized view of design and says that traditional semiconductor scaling and standard processor IP cores are on the way out. The company’s modular RISC-V Instruction Set Architecture with its Custom Compute solutions offers developers feature options that include PPA for any workload through customizing the microarchitecture and the instruction set of a Codasip processor.

Object Toolchain

An object toolchain for RISC-V can save you lots of labor, and if you’re working with a particular partner or provider (more on that below), or within an ecosystem quick-start guide, you’ll likely be provided with an appropriate toolchain for your project. This is a huge timesaver, since it can eliminate the need for a separate debugger, compiler, or archive tool.

SiFive offers its Freedom Studio integrated development environment, based on the Eclipse platform, for use with its RISC-V ecosystem. The Freedom Studio environment is bundled with a pre-built RISC-V GCC Toolchain. The company says that it contains all the tools necessary to compile and debug programs on SiFive products and will support both 32-bit and 64-bit ISAs.

LLVM contains an assembler, disassembler, bitcode analyzer, bitcode optimizer, and basic regression tests. It compiles C, C++, Objective C, and Objective C++ code into LLVM bitcode, and then into object files, using LLVM. It also includes the libc++ C++ standard library and the LLD linker. LLVM does require lots of disk space, up to 20 GB for full builds, so make sure you've got room.

Although this has been a high-level look at the tools and options available in the RISC-V ecosystem right now, it is far from comprehensive. There is a lot to learn, yes, but hopefully you’ve seen that the curve isn’t as steep as you might have feared. The best bit of advice to take away here: a partner is never a bad call, especially when starting out or building complex solutions.

So go ahead, take a RISC-V. (I’m not even sorry for that one.)

Ken Briodagh is a writer and editor with two decades of experience under his belt. He is in love with technology and if he had his druthers, he would beta test everything from shoe phones to flying cars. In previous lives, he’s been a short order cook, telemarketer, medical supply technician, mover of the bodies at a funeral home, pirate, poet, partial alliterist, parent, partner and pretender to various thrones. Most of his exploits are either exaggerated or blatantly false.

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