Speed Through Data with First Ever Fully Customizable RISC-V IP Cores

By Chad Cox

Production Editor

Embedded Computing Design

April 17, 2023


Image Credit: Semidynamics

Semidynamics released a one of a kind 64-bit RISC-V family of cores boosting the ability to transmit copious amounts of information for high-performance computing (HPC) and AI/ML. The cores are process agnostic and utilize Gazzillion technology that was developed for recommendation systems, a must for data center ML.

"Until now, RISC-V processor cores had configurations that were fixed by the vendor or had a very limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters. Our new IP cores enable the customer to have total control over the configuration, be it new instructions, separate address spaces, new memory accessing capabilities, etc.,” said Semidynamics CEO and founder, Roger Espasa.

The Atrevido core was the first of the series to be released. Combining out-of-order scheduling and Gazzillion technology, the core supports current machine learning applications by transmitting data with high-latency using bandwidth memory systems. Gazzillion technology tackles the latency problem with CLX technology, by initiallizing access to distant memory at boosted speeds.

Its 64-bit native data path and 48-bit physical address path supports large memory loads for high-powered workloads, such as HPC. It is Linux ready, has from two to hundreds of cores, and designed to support cache-coherent multiprocessing ecosystems. The cores follow RISC-V Vector Specification 1.0 and the soon to be launched Semidynamics Open Vector Interface.

For more information, visit semidynamics.com.

Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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