Road to embedded world: MIPS Unlocks Power of Edge AI Through Data Movement

By Chad Cox

Production Editor

Embedded Computing Design

April 09, 2024


Road to embedded world: MIPS Unlocks Power of Edge AI Through Data Movement
Image Credit: MIPS

Embedded Computing Design’s Road to embedded world will highlight a host of embedded suppliers who will be showcasing their latest products and technologies at embedded world, April 9th to 11th in Nuremberg, Germany. embedded world is the largest global gathering of its kind. Check back regularly to see where the Road to embedded world takes us.

According to Dave Bell, Senior Director of Product Management, MIPS, at Embedded World 2024 (Booth 4-470), MIPS will exhibit the importance of data movement to deliver the freedom to innovate in Edge AI, without constraints and with more flexibility and customization.

MIPS' architectural design allows for a personalized solution integrating embedded CPUs tightly within the overall SoC framework to manage data flow and memory distribution effectively, eliminating bottlenecks. MIPS cores prioritize simplicity and efficiency, leading to smaller code sizes ideal for edge applications, optimizing storage, and enhancing overall system performance including consistent latency across end-to-end systems.

The cores can simply be integrated with other processors, accelerators, and compute subsystems, all while enabling customization to accommodate the distinct needs of embedded applications. This tighter integration leads to fewer holdups and lower overhead associated with data sharing and movement.

At the core of enabling better data movement is MIPS’ unique multi-threading capabilities, which enable multiple software threads to efficiently execute in parallel.

By adopting more recent strategies in multi-threading, hardware can seamlessly alternate between operations from different threads of execution on each processor cycle without incurring any extra overhead. Consequently, every CPU cycle can effectively execute an operation. Furthermore, in a superscalar CPU architecture, which supports multiple concurrent operations, even for a single thread, the hardware can execute multiple instructions for two or more distinct threads simultaneously within the same cycle. This capability is known as simultaneous multi-threading (SMT).

Booth Highlights of Multi-Threading Capabilities:

Software model of the multi-threaded MIPS P8700 CPU running on a simulation environment

  • The MIPS RISC-V P8700 CPU combines a deep pipeline with multi-issue Out-of-Order (OoO) execution and simultaneous multi-threading to deliver outstanding computational throughput. The simulation environment provides a platform for exploration and early application development.

Demo of MIPS’ multi-threading capabilities of the MIPS P8700 multiprocessor when used with an embedded application such as an Automotive Telematics Server

  • The primary application running on the CPU is an automotive telematics server with a MIPS RISC-V P8700 multiprocessor at its heart, aggregating data from various electronic control units (ECUs) distributed throughout the vehicle. With 2-way simultaneous multi-threading, the CPU can efficiently execute multiple application threads concurrently, to maximize the utilization of the CPU resources for optimal performance per silicon area and power consumption.

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Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.

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