Altera’s Agilex FPGA Portfolio Now in Full Production with Major Performance Upgrades
October 01, 2025
News
Highlights from Altera at Innovators Day 2025 included a 2.5× density boost in Agilex 5 D-Series devices, faster DDR5/LPDDR5 memory interfaces, and the introduction of Visual Designer Studio in Quartus Prime v25.3 to streamline design integration. Altera revealed significant updates to its Agilex FPGA portfolio and design tools.
Agilex FPGA Portfolio Updates:
Agilex FPGA’s:
- Complete Agilex portfolio now in production, including Agilex 5 and Agilex 3 SoC FPGAs with integrated Arm subsystems for edge AI and hardware-software co-processing
Agilex 5 D-Series:
- Up to 2.5× higher logic density (1.6M LEs), greater DSP ratios, and enhanced memory throughput for comprehensive workloads such as edge AI inference, 4K/8K video, and 5G/6G
Enhanced Memory Interfaces:
- DDR5 speeds up to 5,600 MT/s and LPDDR5 up to 5,500 MT/s, a ~25% boost over prior specs
Security:
- Post-quantum cryptography (PQC) secure boot integrated into Agilex 5 D-Series
Developer Tools Updates:
Quartus Prime v25.3:
- Quicker compile times, concentrated resource usage, and higher efficiency
New Visual Designer Studio:
- Drag-and-drop design integration tool cuts FPGA design start times
Altera builds secure scalable solutions for the following applications edge AI, aerospace/defense, communications, and data center.
For more information, visit altera.com.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
