Hybrid DSP From CEVA Adds Controller Functionality

January 04, 2019


Hybrid DSP From CEVA Adds Controller Functionality

CEVA has developed the CEVA-BX hybrid DSP-controller, specifically aimed at voice, video, communication, sensing, and digital signal control applications.

Many IoT applications, particularly those serving consumer, automotive, and industrial markets require both digital signal processing (DSP) capability, as well as digital signal control. The DSP part is to handle things like noise reduction and speech recognition, while digital signal control is used for PHY and motor control, as well as sensor-fusion.

Having all that logic in one device would be an advantage, and that is what’s offered by the CEVA-BX hybrid DSP-controller. CEVA, a licensor of signal processing platforms and AI processors, has developed this part aimed specifically at voice, video, communication, sensing, and digital signal control applications.

The CEVA-BX combines low power with the high-level programming and compact code size requirements of a large control code base. Using an 11-stage pipeline and a five-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz using common standard cells and memory compilers. The part’s instruction-set architecture (ISA) supports single-instruction, multiple-data (SIMD), common in neural network inference, noise reduction, and echo cancellation, as well as half-, single-, and double-precision floating-point units for high accuracy sensor fusion and positioning algorithms.

The CEVA-BX is initially offered in two configurations: the BX1 with one 32- by 32-bit MAC and quad 16- by 16-bit MACs, and the BX2 with quad 32- by 32-bit MACs and octal 16- by 16-bit MACs. The BX2 can handle intensive workloads like 5G PHY control, multi-microphone beamforming, and neural networks for speech recognition, with up to 16 GMACs/x. The BX1 serves low to mid-range applications, such as cellular IoT, protocol stacks, and always-on sensor fusion, with up to 8 GMACs/s. Security is addressed using dedicated trusted execution modes.

The family is accompanied by a software development tool chain, including an LLVM compiler, Eclipse-based debugger, DSP and neural-network compute libraries. The cores are available now to lead customers and by end of Q1/2019 for general licensing.