Lattice Launches the Propel Integrated FPGA Design Environment
June 03, 2020
Designed for designers of all skill levels, the Propel framework provides a GUI so that users can drag and drop IP blocks then allow the tool to automatically optimize the design layout.
Lattice Semiconductor has released Lattice Propel, an integrated FPGA hardware and software design environment that allows engineers to develop applications from scratch using a library of IP and peripherals. Designed for designers of all skill levels, the Propel framework provides a GUI so that users can drag and drop IP blocks then allow the tool to automatically optimize the design layout. It also supports script-level editing for more granular control and updating existing designs.
To support both hardware and software development in a single solution that will accelerate time to market, Propel consists of two components: Propel Builder and Propel SDK.
Propel Builder is the IP integration environment that includes GUI and command-line tools. It provides access to an IP server that contains eight processor and peripheral IP cores, including an RV32I-compliant RISC-V core. All cores are compatible with the AMBA interconnect specification.
Propel SDK includes industry-standard software development tools, libraries, and board support packages for application build, compile, and debug.
The Propel design environment is available now for Lattice customers. More information, including a 10-minute “Hello, World!” demo, is available at https://www.latticesemi.com/propel.