OneSpin Notches Up Formal Verification with Connectivity XL
January 31, 2019
Product
Enables Top-Level Formal Connectivity Verification for Multi-Billion Gate SoCs
OneSpin Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), today unveiled the latest entry in its app library –– the Connectivity XL App –– extending the benefits of formal connectivity checking to 7nm, multi-billion gate system-on-chip (SoC) designs.
The Connectivity XL App has orders of magnitude higher capacity and faster runtime compared to traditional formal connectivity checking, verifying chips with more than one-million connections, 60-million module instances and 30,000 modules.
Connectivity XL automatically generates detailed connectivity specification tables from abstract connectivity specs through a dedicated checking engine that integrates structural and formal analysis to perform on-the-fly, automated abstractions. This reduces the time and effort to specify intended connectivity for large designs.
“Connectivity checking is a well-known and appreciated formal app,” says Dr. Raik Brinkmann, OneSpin Solutions’ president and chief executive officer (CEO). “However, the existing paradigm doesn’t scale with the increase in gate count and complexity of heterogeneous architectures supporting artificial intelligence, machine learning and 5G applications. Connectivity XL offers a unique, innovative approach that further automates formal connectivity checking while scaling to the largest, modern SoCs.”
Connectivity Checking and Connectivity XL
Specifying and verifying a modern SoC’s connections under all possible configurations is daunting because it contains complex subsystems built with hundreds of thousands of instances of highly configurable modules and IP blocks. Heterogeneous hardware platforms add another dimension with more flexibility and adaptability.
Simulation verification is incomplete and less efficient than formal verification even in less complex scenarios. Traditional formal connectivity checking solutions do not scale to these problems either. Slow formal proofs often return inconclusive results requiring extra engineering effort. Creating connectivity specification tables for more than one-million connections is tedious, time consuming and error prone.
The Connectivity XL App eliminates these problems. It enables top-level formal connectivity verification for multi-billion gate SoCs, automates the tedious, time-consuming and error-prone process of creating connectivity specification tables and reduces table maintenance and reuse effort.
The Connectivity XL App supports verification of direct, delayed, conditional and other connection types and enables verification of routing of global signals such as clock, reset and scan enable, I/O pads multiplexing and IP integration. Its focused structural debug information points to the portion of the connection path causing failure, crucial to debugging connectivity checks with thousands of signals.
Abstract connectivity specifications are supported, as is leveraging IP integration rules, naming conventions and multiple module instantiations. Connectivity XL performs checks on abstract specifications to report inconsistencies. It generates detailed, traditional connectivity specification tables by automatically detecting multiplexing conditions, delays and inversion of polarity, and offers localized structural debug information for failing connectivity checks.
OneSpin will demonstrate Connectivity XL in booth #301 during DVCon U.S. Monday, February 25, through Wednesday, February 27, at the DoubleTree Hotel in San Jose, Calif. Representatives from one large semiconductor company will be available in OneSpin’s booth Tuesday and Wednesday from 4:30 p.m. until 5:30 p.m. to describe how they deployed Connectivity XL once their formal tool encountered capacity issues on a 7nm SoC design. With Connectivity XL, they reached conclusive proofs for more than one-million deep connections, while also reducing the effort to create and update specification tables.
Representatives from OneSpin will be available during DVCon China’s poster session to discuss a Connectivity XL implementation, “Scaling Formal Connectivity Checking to Multi-billion Gate SoCs with Specification Automation.” DVCon China will be held Wednesday, April 17, at the Crowne Plaza Hotel Century Park in Shanghai, China. The poster session will be held from 10:45 a.m. until 11:15 a.m.
Availability and Pricing
The OneSpin Connectivity XL App is shipping now. Pricing is available upon request. To learn more about Connectivity XL, visit https://bit.ly/2Gcs9Cz
OneSpin has direct sales channels in the United States, Europe and throughout Asia, backed by a variety of customer service and support options including on-site training, hotline support and consulting services.
About OneSpin Solutions
OneSpin Solutions has emerged as a leader in formal verification through a range of advanced electronic design automation (EDA) solutions for digital integrated circuits. Headquartered in Munich, Germany, OneSpin enables users to address design challenges in areas where reliability really counts: safety-critical verification, SystemC/C++ high-level synthesis (HLS) code analysis and FPGA equivalence checking. OneSpin’s advanced formal verification platform and dedication to getting it right the first time have fueled dramatic growth over the past five years as the company forges partnerships with leading electronics suppliers to pursue design perfection. OneSpin: Making Electronics Reliable.
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