Cadence Powers AI Evolution with Advanced LPDDR6/5X Memory IP System Solution
July 18, 2025
News
Cadence released its LPDDR6/5X memory IP system solution developed to function at 14.4Gbps, a 50 percent increase than prior LPDDR DRAM. The Cadence LPDDR6/5X memory IP system solution allows scaling of AI infrastructure to promote memory bandwidth, and volume demands of next-generation AI LLMs, agentic AI, and other process intense workloads for several verticals.
“The evolution of data centers from HPC compute virtualization to AI training and inference at scale has driven a massive buildout of AI infrastructure, and designing for efficient data movement via memory interfaces has never been more crucial. LPDDR6 has emerged as a key enabler of accelerated compute, providing the speed, bandwidth, power profile and capacity needed to efficiently perform AI inference,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence.
The Cadence IP for the JEDEC LPDDR6/5X standard includes an innovative PHY architecture with a high-performing controller engineered to optimize power, performance, and area (PPA) while supporting both LPDDR6 and LPDDR5X DRAM protocols.
It supports the Arm AMBA AXI bus and is delivered as a soft RTL macro for customization within features, power, area, and performance. The solution also includes the LPDDR6 Memory Model, which allows designers the ability for complete verification ensuring that system-on-chip (SoC) designs are compatible with the latest JEDEC interface standard. It is ideal for AI, mobile, consumer, enterprise HPC, and cloud data center applications.
For more information, visit cadence.com.
Chad Cox. Production Editor, Embedded Computing Design, has responsibilities that include handling the news cycle, newsletters, social media, and advertising. Chad graduated from the University of Cincinnati with a B.A. in Cultural and Analytical Literature.
