Mouser Product of the Week: AMD / Xilinx Spartan UltraScale+ FPGAs
November 03, 2025
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Demanding, safety-critical applications today, such as medical equipment, imaging, factory automation and robotics, smart cities, IIoT gateways and edge appliances, and wireless infrastructure, rely on cost-optimized solutions that leverage low-power, flexible configurations, high I/O counts, and more.
Designed for a range of embedded, industrial, and edge applications, the AMD/Xilinx Spartan UltraScale+ FPGAs provide programmable logic, simplified connectivity, and advanced security. The Spartan UltraScale+ FPGAs are designed to bring FPGA performance to the aforementioned applications built on the UltraScale+ architecture.
The AMD / Xilinx Spartan UltraScale+ FPGAs in Action
The Spartan UltraScale+ FPGAs are ideal for developers looking to optimize I/O expansion, sensor processing and control, and board management, with densities ranging from 11K to 218K logic cells and support for up to 572 I/Os.
The Spartan UltraScale+ FPGA family supports the AMD Vivado design software for AMD adaptive SoCs and FPGA, which includes Design Entry, Synthesis, Place and Route, Verification/Simulation tools. The tools are designed to complement and provide integration across other AMD devices: Artix UltraScale+ FPGAs, Artix 7 FPGAs, Spartan 7 FPGAs, and Spartan 6 FPGAs.
Highlighting performance, the Spartan UltraScale+ FPGAs feature up to 30% power reduction using 16nm FinFET technology, as well as power efficiency through hardened DDR and PCIe interfaces. Also, according to the company, the FPGAs support the highest I/O-to-logic-cell ratio in the AMD Cost-Optimized Portfolio (COP).
For connectivity and flexible interfaces, the FPGAs are equipped with a wide I/O voltage support from 1.2V to 3.3V, high-speed 16.3Gb/s transceivers, and simplified connectivity with PCIe Gen4, MIPI D-PHY, and LPDDR4x/5 memory.
Getting Started with the AMD / Xilinx Spartan UltraScale+ FPGAs
The Spartan UltraScale+ FPGAs support additional development and integration via an end-to-end development environment with the previously mentioned Vivado tools for spanning synthesis, place and route, simulation, and debug. The single IDE also supports a broad portfolio of multiple process nodes, including 28nm, 20nm, 16nm, and 7nm. The IDE is also designed to minimize onboarding time and maximize productivity.
For security, the FPGAs leverage advanced security features designed to protect intellectual property (IP), prevent hardware and software tampering, and maximize system uptime.
For a closer look at the Spartan UltraScale+ FPGAs from AMD/Xilinx, check out the video below:
Additional Resource: https://www.mouser.com/new/xilinx/xilinx-spartan-ultrascale-fpgas/
Tiera Oliver, Assistant Managing Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She develops content and constructs ECD podcasts, such as Embedded Insiders. Before working at ECD, Tiera graduated from Northern Arizona University, where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student-led newspaper, The Lumberjack.
