Pentek, Inc. introduced the Quartz Model 5550, an eight-channel A/D and D/A converter, 3U OpenVPX board based on the Xilinx Zynq UltraScale+ RFSoC and aligned to the SOSA Technical Standard. The Model 5550 is ideal for many communications, electro-optical, electronic warfare, radar, and signals intelligence applications.

A key feature of the Model 5550 is the connector technology that enables one of the major goals of SOSA reference architecture, backplane only I/O. The Model 5550 incorporates the ANSI/VITA 67.3D VPX Backplane Interconnect standard for both coaxial RF and optical I/O. In addition, the Model 5550 includes a 40GigE interface and a shelf-management sub-system that are also required in the SOSA reference architecture.

The Model 5550 uses the Model 6001 QuartzXM eXpress module containing the RFSoC FPGA and all needed support circuitry implemented on a carrier module designed to align with the technical standard for the SOSA reference architecture. This allows upgrades to third generation RFSoC modules when available.

Factory Installed IP Advances Development

The Model 5550 is pre-loaded with a suite of Pentek IP modules to provide data capture and processing solutions for many common applications. Modules include DMA engines, DDR4 memory controller, test signal and metadata generators, data packing, and flow control. The board comes pre-installed with IP for triggered waveform and radar chirp generation, triggered radar range gate selection, wideband real-time transient capture, flexible multi-mode data acquisition, and extended decimation. For many applications, the Model 5550 can be used out-of-the-box with these built-in functions, requiring no FPGA development.

Data Conversion and Analog I/O

The front end accepts analog IF or RF inputs on eight coax connectors located within a VITA 67.3D backplane connector. After balun coupling to the RFSoC, the analog signals are routed to eight 4 GSPS, 12-bit A/D converters. Each converter has built-in digital downconverters with programmable 1x, 2x, 4x and 8x decimation and independent tuning. The A/D digital outputs are delivered into the RFSoC programmable logic and processor system for signal processing, data capture, or for routing to other resources. A stage of IP based decimation provides another 16x stage of data reduction, ideal for applications that need to stream data from all eight A/D's.

Eight 4 GSPS, 14-bit D/A converters deliver balun-coupled analog outputs to a second VITA 67.3D coaxial backplane connector. Four additional 67.3D coaxial backplane connections are provided for clocks and timing signals.

Expandable I/O

The Model 5550 also uses the VITA-67.3D backplane connector for eight 28 Gb/sec duplex optical lanes to the backplane. With two built-in 100 GigE UDP interfaces or a user-installed serial protocol in the RFSoC, the VITA-67.3D backplane interface enables gigabit communications independent of the PCIe interface.

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