Spectrum Monitoring of Very Wide-bandwidth (4.096 GS/s Complex) Signals

August 27, 2024

Sponsored Story

Enclustra was approached by a customer with an idea to design a solution for monitoring the frequency spectrum of wireless telecommunication signals for systems security, i.e., to detect unwanted activity in the spectrum. The unwanted activity could occur at any frequency or time using any communication protocol. With today’s technology in mind, these requirements meant monitoring the frequency range of multiple GHz at a high resolution. Despite the challenging setup, Enclustra's expertise made this project a perfect fit.

Customer Challenge 

As a proof of concept, the customer required a system that constantly monitors the 4.096 GHz bandwidth at a resolution lower than 50 kHz. There aren’t many hardware platforms that can handle processing signals at this speed - this would be a significant challenge even in a modern ASIC. Considering this, Enclustra opted for one of the newest products of AMD, their Zynq UltraScale+ RFSoC device.

The Solution

Enclustra's team fitted the full proof-of-concept system on a single device – both a signal transmitter for generating test signals and signal receiver for computing the spectrum. The FFT size had to be huge and process 8 samples per clock cycle: 131’072 points, which resulted in 31.25 kHz resolution, meeting the < 50 kHz resolution requirement. To manage this, a huge amount of optimization to minimize FPGA resources was required: using linear interpolation to reduce LUT sizes, exploiting function symmetry to reduce LUT sizes, sharing LUT outputs between multiple places, etc.

The clock frequency was 512 MHz to handle the GHz signal processing. BRAM and URAM utilization were very high, which made the timing closure around BRAMs/URAMs challenging.

Another challenge was data reduction. The raw spectrum data (+ metadata) was 64 bits per sample at 4.096 GS/s (512-bit bus on a 512 MHz clock results in 262.144 Gbps). Since no CPU can handle that amount of data, the customer provided an algorithm to discard the data they did not require.

The Result

4.096 GS/s complex signal (equivalent to 8.192 GS/s real signal) monitoring proof-of-concept was implemented on the AMD Zynq™ UltraScale+™ RFSoC device, running at a 512 MHz clock. The system included both transmitter and receiver on a single device, which asked for sophisticated optimization of resource usage. The achieved signal monitoring resolution was 31.25 kHz, well below the initial requirements. 

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