ST MCU sports two cores and two wireless media

February 22, 2018


ST MCU sports two cores and two wireless media

Aimed at smart/IoT products, the STM32WB contains dual Arm cores.

The amount of integration on today’s microcontrollers (MCUs) continues to surprise me. Seemingly, every function you might want on the device is now there. The latest example is STMicroelectronics’ STM32WB MCU sports two processor cores, two different wireless media, and offers very low power consumption. Such a device is suitable for a host of smart connected applications, including like digital-home products, wearable electronics, smart lighting, and smart sensors.

More aptly named a system-on-chip (SoC), the STM32WB is designed with an Arm Cortex M4 core and a Cortex M0+ core. The latter core can offload the main processor (the M4) and offer real-time operation on the Bluetooth Low Energy (BLE) 5 and IEEE 802.15.4 radios. Other wireless protocols can also run concurrently, including OpenThread, ZigBee, or proprietary protocols, all aimed at an enhanced IoT experience. The configuration lets designers manage the user application and the radio separately to maximize performance and power efficiency.

The M0+ contains certified protocol stacks including ST’s OpenThread stack and the Bluetooth 5 stack with Mesh 1.0 support, which comes with multiple profiles. The radio’s generic HCI and Media Access Control (MAC) layer gives developers the flexibility to use their own choice of Bluetooth Low Energy (BLE) stack, or other IEEE 802.15.4 proprietary stacks.

Security features include embedded customer-key storage, an elliptic curve encryption engine for Public Key Authorization (PKA), and hardware support for AES 256-bit cryptography. Designers can also future-proof products in the field, leveraging Secure Firmware Update (SFU) and support for Root Secure Service (RSS) to authenticate Over the Air (OTA) updates.

Various configurations are available, including a 48-pin UQFN, a 68-pin VQFN, or a 100-pin WLCSP with up to 72 general-purpose I/Os (GPIO). Each can be specified with any of three memory configurations, with a choice of 256 kbytes of flash memory and 128 kbytes of RAM; 512 kbytes flash and 256 kbytes RAM; or 1 Mbyte flash and 256 kbytes RAM.