ImperasDV Verification Solutions Certified with Synopsys Functional Simulation and Debug Tools for RISC-V
April 10, 2023
Imperas Software Ltd and Synopsys, Inc. announced a collaboration to accelerate verification of RISC-V processors utilizing ImperasDV verification platforms, and Synopsys' VCS simulation and Verdi debug tools. The partnership will ease time constraints by streamlining RISC-V verification tasks applying to components supplied by both partners.
"RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimized processors," said Kiran Vittal, senior director of Partner Alliances Marketing for Synopsys EDA Group. "Our collaboration with Imperas, leveraging Synopsys' leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence."
ImperasDV is a verification IP designed for RISC-V processors and delivers architectural validation test suites needed to ensure designers their hardware implementations coincide with the software environment supporting RISC-V. The IP includes native support for the open standard RISC V Verification Interface (RVVI) and operates using a 'lock-step-compare' co-simulation methodology for thorough processor verification.
To close, Simon Davidmann, CEO at Imperas Software Ltd said, "The Imperas reference models and simulation technology are structured for close integration within co-simulation and emulation environments. With this latest collaboration with Synopsys, our mutual customers can leverage all the advantages of the ImperasDV verification solutions with the advanced innovations in Synopsys VCS high performance simulation and Verdi debug platform for a complete SystemVerilog 'lock-step-compare' flow with efficient debug for RISC V verification."
For more information, visit imperas.com.