Inflection point for RISC-V: The 7th RISC-V workshop in Silicon Valley

By Larry Lapides

VP Sales

Imperas Software Ltd.

December 11, 2017

The lead announcement for the workshop was from Western Digital: they are starting to transition all their processors, currently around 1 billion shipped per year, to RISC-V.

The 7th RISC-V Workshop was held in Silicon Valley last week, hosted by RISC-V Foundation founding member Western Digital (WD). Each workshop has a different feel to it, and this one seems to be the inflection point in RISC-V maturity. Whereas past workshops felt a bit like a revival tent meeting, with most everyone caught up in the religion of RISC-V, at this workshop there was also a strong sense of turning this into a business. 

The lead announcement for the workshop was from Western Digital: they are starting to transition all their processors, currently around 1 billion shipped per year, to RISC-V. They anticipate that their first RISC-V-based devices will be delivered to end users in about two years.  Perhaps the most interesting element of the announcement was that WD is doing this not to save money, but because of the flexibility and potential for product innovation offered by the RISC-V architecture. 

From the perspective of company participation in the RISC-V community, there are now over 70 companies that have joined the RISC-V Foundation, plus more than 30 individual members.  That is huge membership growth in the two years since the RISC-V Foundation was formed, or even in the three years since the University of California, Berkeley released the initial RISC-V materials. More than those were represented at the Workshop, with over 120 different companies and over 25 universities composing the attendee list. 

While it is still “early days” for RISC-V – there have been only about 20 chips fabricated with RISC-V cores, and most of those are just test chips, none have really been “used in anger” as my English colleagues would say – it is also clear that the ecosystem is progressing. There were processor IP announcements from Andes, Codasip, Esperanto, and SiFive, presentations and other support from debugger companies like Ashling, Lauterbach, and Segger, new OS support from Express Logic, Micrium, and others, tool chain progress for both GNU and LLVM, and tools and services from Imperas, Intrinsix, and UltraSoC. 

All these companies participating in the RISC-V community, contributing to the RISC-V community, investing in the RISC-V community, are doing this not because they believe in open source architectures, but because they believe that this open source architecture, with a viable ecosystem, can be commercially successfully. 

For our part, Imperas sees in RISC-V an opportunity to leverage our technologies in processor modeling, software simulation, and software development, debug, and test tools to help RISC-V be successful. At this Workshop, Imperas presented information about our collaboration with Microsemi on virtual platforms of Microsemi Mi-V RISC-V platforms running FreeRTOS (the “Mi-V FreeRTOS EPK”), announced OVP Fast Processor Models of the Andes N25 and NX25 processors, and announced our RISC-V Processor Developer Suite

The RISC-V Processor Developer Suite contains the base RISC-V models and tools necessary to validate and verify the functionality of a RISC-V processor. These RISC-V models are provided as source, and are easily extendable to support custom instructions and other features. The RISC-V Processor Developer Suite also enables the early estimation of timing performance and power consumption for the processor. This integrated suite of models and tools is designed to help both processor IP developers with internal efforts on RISC-V cores, and the users of those cores building software to run on RISC-V based silicon. 

While the next RISC-V Workshop is in May, in Barcelona, there is a RISC-V Day in Tokyo December 18th, and a day of RISC-V presentations plus a RISC-V exhibit area at Embedded World Feb 27 – Mar 1 in Nuremberg. 

Larry Lapides is Vice President of Sales at Imperas Software. Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.

Specialties: Sales and marketing for startups.

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