The QorIQ Layerscape Technology

By Konrad Z?pf

Deputy Director

TQ-Systems GmbH

April 03, 2020


The QorIQ Layerscape Technology

This name stands for the combination of an energy-efficient Arm?-Core and the high-speed peripherals of the QorIQ? Power? architecture.

In April 2013, NXP (formerly Freescale) published information that a new processor generation, called Layerscape, will be launched in addition to the already known and successful Power® architecture on the market. At that time, it was not yet known that these newly designed, Arm®-Core-based CPUs would replace the Power® architecture. In mid-2014 NXP announced that the Power® architecture roadmap would be discontinued and replaced by QorIQ®-Layerscape technology in the long term. The first CPU derivative, launched in 2013, consisting of three pin-compatible variants of the LS1021A. Roadmap information followed in early 2014. From here on, things went full steam ahead and further CPU derivatives were announced. As the second CPU, the LS2088A was introduced to the market. However, due to its special features specifically designed for the server market, this is not as widely used as the LS1088A, LS1043A, or the LS1046A series announced in 2015. At the end of 2018 NXP then released the LS1028A. This year the high-end CPU derivative LX2160A, which promises many new features in the field of network technology with the features already known today, will be launched.

The QorIQ® Layerscape technology

This name stands for the combination of an energy-efficient Arm®-Core and the high-speed peripherals of the QorIQ® Power® architecture. The Arm® CPU core is connected to the communication unit via a new bus system "Cache Coherent Interconnect" (CCI400). This combination forms an ideal platform for demanding data communication tasks. By integrating Freescale's well-known QUICC Engine technology (also known as QE), the Layerscape CPUs can continue to be used in follow-up projects where this QE has been used up to now. An advantage of this architecture is that both big-endian (applied to the Power® architecture) and little-endian (applied to the general Arm® technology) are supported on these Layerscape processors. This means that applications and computational operations previously used on the Power® architecture, as well as software previously used, are easier to port and use.

Features of the LS1021A family

The embedded CPU LS1021A, with the variants LS1020A and LS1022A, is optimized for system developers who want to develop highly efficient platforms on the latest system architecture for processing high data volumes. The LS102xA CPU family offers a dual Cortex-A7 core with ECC-protected L1 and L2 cache for maximum reliability. The average power consumption of the processor is 3-4 W. With the LCD controller integrated in the LS1021A processor, system developments can also be achieved that place demands on an operating unit with display and touch screen. This results in a great cost advantage. In addition to 3x Gigabit Ethernet, 2x PCIe Gen2, USB 2.0 host / USB 3.0 OTG controller and ten UARTs, users can also use up to four FlexCANs (only with the LS1021A) for communication. Further functional units can be connected via SATA, SDIO, SPI, I2C and I2S.

LS1012A: High-speed with only 1 W.

The LS1012A is based on the new 64-bit Cortex-A53 QorIQ®-Layerscape technology and is ideally suited for robust and industrial routers, gateways and data loggers. In addition to a 16-bit wide DDR3L SDRAM interface, which allows expansion up to 1GB, users can also use a QSPI NOR Flash with a maximum memory size of 256 MB as a boot device. A power dissipation of 1 W in connection with the High-Speed interfaces implemented in the CPU promise a wide range of possible applications. Applications can be created in which both very low energy consumption and secure and fast data communication are required. Besides 2x Gigabit Ethernet, PCIe 2.0, SATA3, and USB 3.0, UARTs, I2C and I2S, are also available.

10 Gigabit Ethernet with the LS1043A/ LS1046A and LS1088A family

Users benefit from a very powerful platform at attractive conditions. Up to five optimized CPU variants are available for various applications such as networking, industrial automation and control systems with high requirements for fast and secure data communication. The pin-compatible CPUs (LS1046A/26A, LS1043A/23A, and LS1088A) differ in the number of interfaces offered and the number of cores. Depending on the configuration, Cortex-A72 or -A53, each with dual or quad core, or a Cortex-A53 with octal core with a clock rate of up to 1.8 GHz are available. This CPU diversity allows the optimal balance between high CPU computing power, fast data transfer rates and low power dissipation to be selected.

For high-speed communication, up to eight SerDES lanes can be used for the interfaces 2x 10 Gigabit Ethernet, 5x Gigabit, 3x PCIe Gen3, and 1x SATA 3.0. In addition, a maximum of three USB 3.0 high-speed interfaces are offered, as well as UARTs, I2C and GPIOs. DDR4 SDRAM with ECC, one SDIO and two Quad SPI interfaces are available as memory.

TSN and graphics with the LS1028A CPUs.

The Arm® Layerscape LS1028A from the NXP processor family is built on Cortex-A72 technology. Based on this CPU, one of four different pin-compatible CPU derivatives can be selected, depending on the required functionality. The CPUs come as two single core (LS1017A and LS1018A) and two dual core variants (LS1027A and LS1028A). The CPUs LS1017A and LS1027A are for headless systems, i.e. the graphics function is deactivated. The integrated powerful GPU of the LS1018A and LS1028A supports 4K displays. With a clock rate of up to 1.3 GHz, this CPU family offers a comprehensive and scalable platform with low power dissipation.

A TSN-capable Gigabit Ethernet switch with four ports is available for fast and real-time data communication. Additionally, two interfaces for Gigabit Ethernet (1G/2.5G) can be used. The 2.5GB Ethernet interface is also TSN-compatible. In addition to UARTs, SDIO, and I²C, all CPUs offer the following interfaces: up to 2x PCIe Gen3, 2x USB 3.0, 1x SATA 3.0, and 2x CAN. Up to 4 GB DDR4 SDRAM plus ECC support and eMMC memory are available. In addition, up to 512 MB NOR Flash can be connected via two QSPI interfaces. These CPUs are particularly suitable for industrial automation and control applications based on TSN, networking and applications requiring fast, real-time and secure data communication in combination with graphics.


The LX2160A with 100 Gigabit Ethernet.

The LX2160A high-end communications processor provides 24 high-speed SerDES lanes with up to 25 GHz for high-speed data communications. The SerDES lanes can be used for SATA, PCIe, or Ethernet. Computing performance can be scaled over a wide range thanks to eight, twelve or sixteen Cortex-A72 cores. Up to two 100 Gigabit Ethernet interfaces can be set up with this NXP CPU. DDR4 SDRAM with ECC support can be connected via two 72-bit wide memory interfaces. In addition to two CAN-FD, eight I2C and SPI, two USB 3.0 have been integrated into the CPU. With this CPU, users can meet their requirements for servers, high-end camera transmissions and satellite technology to an unprecedented extent. For a protected and secure data transmission, extensive security functions can be accessed.

Table 1: Short overview Layerscape series

Within each family, the QorIQ®-Layerscape CPU product generation in turn consists of pin-compatible CPU derivatives, thus combining numerous functions and performance classes for future-oriented developments. Depending on the design requirements, a suitable core can be selected from the respective CPU family. Thus, starting with a dual Cortex-A7 core up to sixteen Cortex-A72 cores, this CPU series is the ideal basis for applications from a wide range of areas and applications in which the future-oriented network technology is to be used.

TQ-Systems has taken advantage of all the CPU advantages and based on this, has developed the largest product portfolio of embedded modules on the market. Each module provides 100% of all available signal pins, so that the user is not subject to any limitations when using the interfaces and their pin multiplexings.