Rambus Delivers CXL 2.0 Controller with Zero-Latency IDE

By Taryn Engmark

Assistant Editor

Embedded Computing Design

October 06, 2021


Rambus Delivers CXL 2.0 Controller with Zero-Latency IDE

Delivering security at speed in Compute Express Link™ (CXL) is critical to solving the bandwidth bottleneck in data center infrastructure. Integrity and Data Encryption (IDE) monitors and protects against physical attacks on CXL and PCI Express® (PCIe) links. CXL requires extremely low latency to enable load-store memory architectures and cache-coherent links for its targeted use cases.

Rambus Inc. announced CXL 2.0 and PCIe 5.0 controllers available with integrated IDE modules. This controller with a zero-latency IDE, developed by the engineering team from newly-acquired PLDA, delivers security and performance at full 32 GT/s speed.

The built-in IDE modules employ a 256-bit AES-GCM (Advanced Encryption Standard, Galois/Counter Mode) symmetric-key cryptographic block cipher, helping chip designers and security architects to ensure confidentiality, integrity, and replay protection for traffic that travels over CXL and PCIe links. This secure functionality is especially imperative for data center computing applications including AI/ML and high-performance computing.

Key features include:

  • IDE security with zero latency for CXL.mem and CXL.cache
  • Complete CXL 2.0 and PCIe 5.0 interconnect subsystems when controllers are combined with Rambus CXL 2.0 and PCIe 5.0 PHYs

For more information, visit Rambus.