Mixel Announces Availability of the World's First MIPI C-PHY/D-PHY Combo IP Supporting 30 Gbps

By Tiera Oliver

Associate Editor

Embedded Computing Design

September 22, 2020

Mixel Announces Availability of the World's First MIPI C-PHY/D-PHY Combo IP Supporting 30 Gbps

Mixel's IP supports high-performance imaging and display applications

Mixel, a provider of mixed-signal intellectual property (IP), announced that its MIPI C-PHY(SM)/D-PHY(SM) IP, compliant with the MIPI C-PHY v2.0 and MIPI D-PHY v2.5 specifications, is now available.

MIPI D-PHY supports MIPI Camera Serial Interface 2 (CSI-2(SM)) and Display Serial Interface (DSI(SM)) and DSI-2(SM_. According to the company, Mixel is the first IP provider to make this IP available to its customers, with the total aggregate speed reaching over 30 Gbps.

Mixel's MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI transmitter or receiver, supporting both the camera interface CSI-2 v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification.

Mixel's MIPI C-PHY v2.0 supports a speed of 4.5 Gsps per trio, an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18Gbps in their respective modes.

The Mixel MIPI C-PHY/D-PHY Combo IP includes many new features to both the D-PHY and C-PHY that was not available in previous versions of the specifications, namely Spread Spectrum Clocking (SSC), transmit equalization (de-emphasis), and receiver ISI calibration. It also supports new power saving functionality such as HS-TX reduced swing modes and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround that boosts transmission bandwidth in the reverse direction of the MIPI link. The ALP Mode is central to the CSI-2 Unified Serial Link feature that reduces number of interface wires and helps to natively support longer reach. The combo PHY IP not only shares the serial interface pins, but Mixel's implementation also reuses all the MIPI D-PHY functional blocks for the MIPI C-PHY, minimizing area and leakage power.

Mixel was the first IP provider to demonstrate silicon for MIPI D-PHY and MIPI C-PHY. Since then, Mixel's MIPI PHY IP has been silicon-proven in 9 different nodes at 8 different foundries in multiple configurations including the patented RX+ configuration that allows for full-speed, in-system production testing with minimal overhead.

Mixel MIPI C-PHY/D-PHY Combo IP is available now.

For more information, visit https://mixel.com/ip-core

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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