OCP 2019: eSilicon to demonstrate 56G DSP SerDes over a 5-meter cable assembly in Samtec booth

March 12, 2019

Press Release

OCP 2019: eSilicon to demonstrate 56G DSP SerDes over a 5-meter cable assembly in Samtec booth

eSilicon will demonstrate its 7nm FinFET-class SerDes IP product at OCP 2019

eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will demonstrate its 7nm FinFET-class SerDes IP product at OCP 2019.

What

SerDes Demonstration: Samtec booth at OCP, San Jose Convention Center

Thursday-Friday

March 14-15, 2019

Using Samtec ExaMAX Backplane Connector paddle cards and a five-meter ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes.

The demonstration will drive four high-speed SerDes lanes in three configurations:

CPRI NRZ modulation with point-to-point links

50G Ethernet PAM4 modulation with point-to-point links

56 Gbps PAM4 modulation with point-to-point links

Real-time data associated with all channels will also be displayed to demonstrate the robustness and low power of the device, including:

Voltage histograms, pre- and post-DSP

Signal-to-noise ratio (SNR)

Equalization

Bit error rate (BER) monitor

March 14-15, 2019

San Jose, Calif., USA

The 2019 Open Compute Project (OCP) Global Summit brings together more than 3,400 key decision makers, executives, engineers, developers and suppliers. Together, they help grow, drive and support the open hardware ecosystem in, near and around the datacenter and beyond.

About eSilicon

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

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