SmartDV Technologies and Aldec inked an agreement linking SmartDV's Verification IP with Aldec's Riviera-PRO high-performance simulation and debugging tool.

Under terms of the agreement, SmartDV and Aldec will cooperate technically to ensure their respective Verification IP and simulator work together. They agreed as well to jointly market their solutions.

Aldec's Riviera-PRO addresses verification needs of engineers crafting tomorrow's FPGA and SoC devices. The tool enables the testbench productivity, reusability, and automation by combining the simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

SmartDV's Verification IP portfolio is compatible with all verification languages, platforms and methodologies and used throughout a coverage-driven chip design verification flow in simulation, emulation, FPGA prototyping, and formal verification environments. A proprietary, automated compiler-based technology ensures ideal delivery of its offerings compliant with standard protocol specifications for new or evolving applications.

SmartDV and Aldec will exhibit virtually at the 57th Design Automation Conference (DAC) starting Monday, July 20, through Saturday, August 1. The Virtual Expo Hall will be open with Live Chat hours from 10:30 a.m. until 1:30 p.m. PDT. Monday through Wednesday, July 20-22.

For more information, visit: www.aldec.com