CAMBRIDGE, UK – 21 Feb 2019 - UltraSoC, the leading provider of embedded analytics for the RISC-V ecosystem, today announced full support within its embedded analytics architecture for Western Digital’s RISC-V SweRV Core™ and associated OmniXtend™ cache-coherent interconnect. The two companies have worked together to create a debug and on-chip analytics ecosystem that will support the requirements of both Western Digital’s internal development teams, and third parties choosing to adopt the SweRV Core for their own applications.

“Western Digital has proven to be a powerful driving force within the RISC-V ecosystem, with a visionary approach encompassing processors that are closely tailored to their target applications,” said Rupert Baines, UltraSoC CEO. “The SweRV concept is a compelling one, and we’re extremely proud to have been selected to support it at an early stage of its evolution.”

SweRV is an open source RISC-V core intended to accelerate development of open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, allowing it to create processors that are purpose-built for data-centric applications. Every storage product the company ships contains some kind of processor, and the company has committed to transitioning one billion of these cores to the RISC-V architecture.

UltraSoC launched the industry’s first – and still only – commercial RISC-V processor trace solution in June 2017, and is committed to supporting both standards-based and proprietary debug and analytics approaches. Trace functionality is a key tool for system developers, allowing the behavior of a program to be viewed in detail. UltraSoC’s embedded analytics technology is uniquely capable of supporting very powerful multicore system-on-chip (SoC) implementations, and enables seamless development and debug of systems containing multiple different types of processor: known as heterogeneous systems.

Western Digital's RISC-V SweRV Core is based on a two-way superscalar design, with a 32-bit, nine-stage pipeline core that allows several instructions to be loaded at once and execute simultaneously. It is a compact, in-order core and is expected to run at around 5 CoreMarks/Mhz. Its power-efficient design offers clock speeds of up to 1.8Ghz on a 28nm CMOS process technology. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.