SmartDV Announces Support for ARINC Standards with Design and Verification IP

By Tiera Oliver

Assistant Managing Editor

Embedded Computing Design

June 07, 2021

News

SmartDV Announces Support for ARINC Standards with Design and Verification IP

SmartDV Technologies announced support of the ARINC standards with its Design and Verification IP.
 

ARINC standards describe avionics, cabin systems, protocols, and interfaces used by air transport and business aircraft. Per the company, SmartDV's Design IP is currently compliant with the ARINC 664 standard and its Verification IP is compliant with ARINC 419, 429, 664, 818, and 825 standards.

Design IP
SmartDV's configurable and silicon-proven Design IP is pre-verified and delivered in Verilog source code. The comprehensive solution includes lint, clock domain crossing, synthesis, simulation scripts with waiver files, and documentation.

Verification IP
A Verification IP portfolio offered by SmartDV is used in networking, storage, automotive, bus, MIPI, and display chip projects to verify and debug designs. According to the company, the Verification IP is compatible with all verification languages, platforms, and methodologies supporting all simulation, emulation, and formal verification tools used in a coverage-driven chip design verification flow.

SmartDV's proprietary, automated compiler-based technology is designed to ensure suitable delivery of its offerings compliant with ARINC standards and other protocol specifications for new or evolving applications. It also comes with SmartDV's Automation Tool Suite that provides testbench generation and visual protocol debugging.

The SmartDV Design and Verification IP portfolio for ARINC standards is available now. Pricing is available upon request.

For more information, visit: https://www.smart-dv.com

Tiera Oliver is the assistant managing editor at Embedded Computing Design. She is responsible for web content editing, product news, and story development. She also manages, edits, and develops content for ECD podcasts, including Embedded Insiders.

She utilizes her expertise in journalism and content management to oversee editorial content, coordinate with editors, and ensure high-quality output across web, print, and multimedia platforms. She manages diverse projects, assists in the production of digital magazines, and hosts company podcasts by conducting in-depth interviews with industry leaders to deliver engaging and insightful discussions.

Tiera attended Northern Arizona University, where she received her bachelor's in journalism and political science. She was also a news reporter for the student-led newspaper, The Lumberjack. 

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